Commit 71ab34f7 authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'drm-misc-next-2024-02-22' of git://anongit.freedesktop.org/drm/drm-misc into drm-next



drm-misc-next for v6.9:

UAPI Changes:

- changes to fdinfo stats

Cross-subsystem Changes:

agp:
- remove unused type field from struct agp_bridge_data

Core Changes:

ci:
- update test names
- cleanups

gem:
- add stats for shared buffers plus updates to amdgpu, i915, xe

Documentation:
- fixes

syncobj:
- fixes to waiting and sleeping

Driver Changes:

bridge:
- adv7511: fix crash on irq during probe
- dw_hdmi: set bridge type

host1x:
- cleanups

ivpu:
- updates to firmware API
- refactor BO allocation

meson:
- fix error handling in probe

panel:
- revert "drm/panel-edp: Add auo_b116xa3_mode"
- add Himax HX83112A plus DT bindings
- ltk500hd1829: add support for ltk101b4029w and admatec 9904370
- simple: add BOE BP082WX1-100 8.2" panel plus DT bindungs

renesas:
- add RZ/G2L DU support plus DT bindings

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20240222135841.GA6677@localhost.localdomain
parents 40d47c5f a3baaca4
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/himax,hx83112a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Himax HX83112A-based DSI display panels

maintainers:
  - Luca Weiss <luca.weiss@fairphone.com>

description:
  The Himax HX83112A is a generic DSI Panel IC used to control
  LCD panels.

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    contains:
      const: djn,9a-3r063-1102b

  vdd1-supply:
    description: Digital voltage rail

  vsn-supply:
    description: Positive source voltage rail

  vsp-supply:
    description: Negative source voltage rail

  reg: true
  port: true

required:
  - compatible
  - reg
  - reset-gpios
  - vdd1-supply
  - vsn-supply
  - vsp-supply
  - port

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    dsi {
        #address-cells = <1>;
        #size-cells = <0>;

        panel@0 {
            compatible = "djn,9a-3r063-1102b";
            reg = <0>;

            backlight = <&pm6150l_wled>;
            reset-gpios = <&pm6150l_gpios 9 GPIO_ACTIVE_LOW>;

            vdd1-supply = <&vreg_l1e>;
            vsn-supply = <&pm6150l_lcdb_ncp>;
            vsp-supply = <&pm6150l_lcdb_ldo>;

            port {
                panel_in_0: endpoint {
                    remote-endpoint = <&dsi0_out>;
                };
            };
        };
    };

...
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@@ -14,7 +14,9 @@ allOf:

properties:
  compatible:
    const: leadtek,ltk500hd1829
    enum:
      - leadtek,ltk101b4029w
      - leadtek,ltk500hd1829
  reg: true
  backlight: true
  reset-gpios: true
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@@ -39,6 +39,8 @@ properties:
  compatible:
    items:
      - enum:
          # Admatec 9904379 10.1" 1024x600 LVDS panel
          - admatec,9904379
          - auo,b101ew05
          # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel
          - chunghwa,claa070wp03xg
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@@ -73,6 +73,8 @@ properties:
      - auo,t215hvn01
        # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel
      - avic,tm070ddh03
        # BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel
      - boe,bp082wx1-100
        # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel
      - boe,bp101wx1-100
        # BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L Display Unit (DU)

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description: |
  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
  and RZ/V2L SoCs.

properties:
  compatible:
    oneOf:
      - enum:
          - renesas,r9a07g044-du # RZ/G2{L,LC}
      - items:
          - enum:
              - renesas,r9a07g054-du    # RZ/V2L
          - const: renesas,r9a07g044-du # RZ/G2L fallback

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Main clock
      - description: Register access clock
      - description: Video clock

  clock-names:
    items:
      - const: aclk
      - const: pclk
      - const: vclk

  resets:
    maxItems: 1

  power-domains:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: |
      The connections to the DU output video ports are modeled using the OF
      graph bindings. The number of ports and their assignment are
      model-dependent. Each port shall have a single endpoint.

    patternProperties:
      "^port@[0-1]$":
        $ref: /schemas/graph.yaml#/properties/port
        unevaluatedProperties: false

    required:
      - port@0

    unevaluatedProperties: false

  renesas,vsps:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle to VSP instance that serves the DU channel
        - description: Channel index identifying the LIF instance in that VSP
    description:
      A list of phandle and channel index tuples to the VSPs that handle the
      memory interfaces for the DU channels.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - power-domains
  - ports
  - renesas,vsps

additionalProperties: false

examples:
  # RZ/G2L DU
  - |
    #include <dt-bindings/clock/r9a07g044-cpg.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    display@10890000 {
        compatible = "renesas,r9a07g044-du";
        reg = <0x10890000 0x10000>;
        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
        clock-names = "aclk", "pclk", "vclk";
        resets = <&cpg R9A07G044_LCDC_RESET_N>;
        power-domains = <&cpg>;

        renesas,vsps = <&vspd0 0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };
            port@1 {
                reg = <1>;
            };
        };
    };

...
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