Commit 71bc986c authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-stmmac-ingenic-convert-to-set_phy_intf_sel' 

Russell King says:

====================
net: stmmac: ingenic: convert to set_phy_intf_sel()

Convert ingenic to use the new ->set_phy_intf_sel() method that was
recently introduced in net-next.

This is the largest of the conversions, as there is scope for cleanups
along with the conversion.
====================

Link: https://patch.msgid.link/aQ2tgEu-dudzlZlg@shell.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 7ff14c52 34bf68a6

drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c

+45 −120
Original line number Diff line number Diff line
@@ -35,10 +35,6 @@ 
#define MACPHYC_RX_DELAY_MASK		GENMASK(10, 4)

#define MACPHYC_SOFT_RST_MASK		GENMASK(3, 3)

#define MACPHYC_PHY_INFT_MASK		GENMASK(2, 0)

#define MACPHYC_PHY_INFT_RMII		0x4

#define MACPHYC_PHY_INFT_RGMII		0x1

#define MACPHYC_PHY_INFT_GMII		0x0

#define MACPHYC_PHY_INFT_MII		0x0



#define MACPHYC_TX_DELAY_PS_MAX		2496

#define MACPHYC_TX_DELAY_PS_MIN		20
@@ -68,147 +64,59 @@ struct ingenic_soc_info { 
	enum ingenic_mac_version version;

	u32 mask;



	int (*set_mode)(struct plat_stmmacenet_data *plat_dat);

};



static int ingenic_mac_init(struct platform_device *pdev, void *bsp_priv)

{

	struct ingenic_mac *mac = bsp_priv;

	int ret;

	int (*set_mode)(struct ingenic_mac *mac, u8 phy_intf_sel);



	if (mac->soc_info->set_mode) {

		ret = mac->soc_info->set_mode(mac->plat_dat);

		if (ret)

			return ret;

	}



	return 0;

}

	u8 valid_phy_intf_sel;

};



static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int jz4775_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;

	unsigned int val;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_MII:

		val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |

			  FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_MII);

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n");

		break;



	case PHY_INTERFACE_MODE_GMII:

		val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |

			  FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_GMII);

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n");

		break;



	case PHY_INTERFACE_MODE_RMII:

		val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |

			  FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");

		break;



	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

		val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) |

			  FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII);

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");

		break;



	default:

		dev_err(mac->dev, "Unsupported interface %s\n",

			phy_modes(plat_dat->phy_interface));

		return -EINVAL;

	}

	val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel) |

	      FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT);



	/* Update MAC PHY control register */

	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);

}



static int x1000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int x1000_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_RMII:

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");

		break;



	default:

		dev_err(mac->dev, "Unsupported interface %s\n",

			phy_modes(plat_dat->phy_interface));

		return -EINVAL;

	}



	/* Update MAC PHY control register */

	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, 0);

}



static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int x1600_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;

	unsigned int val;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_RMII:

		val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");

		break;



	default:

		dev_err(mac->dev, "Unsupported interface %s\n",

			phy_modes(plat_dat->phy_interface));

		return -EINVAL;

	}

	val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);



	/* Update MAC PHY control register */

	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);

}



static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int x1830_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;

	unsigned int val;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_RMII:

	val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII) |

			  FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");

		break;



	default:

		dev_err(mac->dev, "Unsupported interface %s\n",

			phy_modes(plat_dat->phy_interface));

		return -EINVAL;

	}

	      FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);



	/* Update MAC PHY control register */

	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);

}



static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)

static int x2000_mac_set_mode(struct ingenic_mac *mac, u8 phy_intf_sel)

{

	struct ingenic_mac *mac = plat_dat->bsp_priv;

	unsigned int val;



	switch (plat_dat->phy_interface) {

	case PHY_INTERFACE_MODE_RMII:

		val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |

			  FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN) |

			  FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII);

		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");

		break;



	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

		val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII);

	val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);



	if (phy_intf_sel == PHY_INTF_SEL_RMII) {

		val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |

		       FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);

	} else if (phy_intf_sel == PHY_INTF_SEL_RGMII) {

		if (mac->tx_delay == 0)

			val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN);

		else
@@ -220,20 +128,29 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat) 
		else

			val |= FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_DELAY) |

				   FIELD_PREP(MACPHYC_RX_DELAY_MASK, (mac->rx_delay + 9750) / 19500 - 1);



		dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");

		break;



	default:

		dev_err(mac->dev, "Unsupported interface %s\n",

			phy_modes(plat_dat->phy_interface));

		return -EINVAL;

	}



	/* Update MAC PHY control register */

	return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);

}



static int ingenic_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel)

{

	struct ingenic_mac *mac = bsp_priv;



	if (!mac->soc_info->set_mode)

		return 0;



	if (phy_intf_sel >= BITS_PER_BYTE ||

	    ~mac->soc_info->valid_phy_intf_sel & BIT(phy_intf_sel))

		return -EINVAL;



	dev_dbg(mac->dev, "MAC PHY control register: interface %s\n",

		phy_modes(mac->plat_dat->phy_interface));



	return mac->soc_info->set_mode(mac, phy_intf_sel);

}



static int ingenic_mac_probe(struct platform_device *pdev)

{

	struct plat_stmmacenet_data *plat_dat;
@@ -293,7 +210,7 @@ static int ingenic_mac_probe(struct platform_device *pdev) 
	mac->plat_dat = plat_dat;



	plat_dat->bsp_priv = mac;

	plat_dat->init = ingenic_mac_init;

	plat_dat->set_phy_intf_sel = ingenic_set_phy_intf_sel;



	return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);

}
@@ -303,6 +220,9 @@ static struct ingenic_soc_info jz4775_soc_info = { 
	.mask = MACPHYC_TXCLK_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,



	.set_mode = jz4775_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_GMII_MII) |

			      BIT(PHY_INTF_SEL_RGMII) |

			      BIT(PHY_INTF_SEL_RMII),

};



static struct ingenic_soc_info x1000_soc_info = {
@@ -310,6 +230,7 @@ static struct ingenic_soc_info x1000_soc_info = { 
	.mask = MACPHYC_SOFT_RST_MASK,



	.set_mode = x1000_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),

};



static struct ingenic_soc_info x1600_soc_info = {
@@ -317,6 +238,7 @@ static struct ingenic_soc_info x1600_soc_info = { 
	.mask = MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,



	.set_mode = x1600_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),

};



static struct ingenic_soc_info x1830_soc_info = {
@@ -324,6 +246,7 @@ static struct ingenic_soc_info x1830_soc_info = { 
	.mask = MACPHYC_MODE_SEL_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,



	.set_mode = x1830_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RMII),

};



static struct ingenic_soc_info x2000_soc_info = {
@@ -332,6 +255,8 @@ static struct ingenic_soc_info x2000_soc_info = { 
			MACPHYC_RX_DELAY_MASK | MACPHYC_SOFT_RST_MASK | MACPHYC_PHY_INFT_MASK,



	.set_mode = x2000_mac_set_mode,

	.valid_phy_intf_sel = BIT(PHY_INTF_SEL_RGMII) |

			      BIT(PHY_INTF_SEL_RMII),

};



static const struct of_device_id ingenic_mac_of_matches[] = {