Commit 71dfa617 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Add missing debug registers for DCN2/3/3.1 



This commit add some missing debug registers for DPCS and RDPC debug.

Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent af864412

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h

+4 −1
Original line number Diff line number Diff line
@@ -147,7 +147,8 @@ 
	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\

	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\

	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\

	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh)

	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh),\

	LE_SF(DPCSTX0_DPCSTX_DEBUG_CONFIG, DPCS_DBG_CBUS_DIS, mask_sh)



#define DPCS_DCN2_MASK_SH_LIST(mask_sh)\

	DPCS_MASK_SH_LIST(mask_sh),\
@@ -231,6 +232,8 @@ 
	SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \

	SRI(DPCSTX_TX_CLOCK_CNTL, DPCSTX, id), \

	SRI(DPCSTX_TX_CNTL, DPCSTX, id), \

	SRI(DPCSTX_DEBUG_CONFIG, DPCSTX, id), \

	SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \

	SR(RDPCSTX0_RDPCSTX_SCRATCH)

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h

+2 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ 
	SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \

	SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \

	SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \

	SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \

	SR(RDPCSTX0_RDPCSTX_SCRATCH), \

	SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\

	SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
@@ -222,6 +223,7 @@ 
	SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \

	SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \

	SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \

	SRI(RDPCSTX_DEBUG_CONFIG, RDPCSTX, id), \

	SR(RDPCSTX0_RDPCSTX_SCRATCH), \

	SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\

	SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)

drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_offset.h

+24 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ 
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2

#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                                               0x292d

#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2

#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG                                                                  0x292e

#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2





// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
@@ -50,6 +52,8 @@ 
#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2

#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c

#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2

#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG                                                                0x293d

#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2

#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940

#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2

#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
@@ -120,6 +124,8 @@ 
#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2

#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                                               0x2a05

#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2

#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG                                                                  0x2a06

#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2





// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
@@ -146,6 +152,8 @@ 
#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2

#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14

#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2

#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG                                                                0x2a15

#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2

#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18

#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2

#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
@@ -216,6 +224,8 @@ 
#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2

#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA                                                               0x2add

#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2

#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG                                                                  0x2ade

#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2





// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
@@ -242,6 +252,8 @@ 
#define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2

#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2aec

#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2

#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG                                                                0x2aed

#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2

#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0

#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2

#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1
@@ -312,6 +324,8 @@ 
#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2

#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA                                                               0x2bb5

#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2

#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG                                                                  0x2bb6

#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2





// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
@@ -338,6 +352,8 @@ 
#define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2

#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2bc4

#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2

#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG                                                                0x2bc5

#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2

#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8

#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2

#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9
@@ -408,6 +424,8 @@ 
#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2

#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA                                                               0x2c8d

#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2

#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG                                                                  0x2c8e

#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2





// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
@@ -434,6 +452,8 @@ 
#define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX                                                              2

#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2c9c

#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2

#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG                                                                0x2c9d

#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2

#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0                                                                   0x2ca0

#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2

#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1                                                                   0x2ca1
@@ -504,6 +524,8 @@ 
#define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2

#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA                                                               0x2d65

#define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2

#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG                                                                  0x2d66

#define mmDPCSTX5_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2





// addressBlock: dpcssys_dpcs0_rdpcstx5_dispdec
@@ -530,6 +552,8 @@ 
#define mmRDPCSTX5_RDPCSTX_CNTL2_BASE_IDX                                                              2

#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2d74

#define mmRDPCSTX5_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2

#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG                                                                0x2d75

#define mmRDPCSTX5_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2

#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0                                                                   0x2d78

#define mmRDPCSTX5_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2

#define mmRDPCSTX5_RDPCSTX_PHY_CNTL1                                                                   0x2d79

drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_0_0_sh_mask.h

+3 −1
Original line number Diff line number Diff line
@@ -70,7 +70,9 @@ 
//DPCSTX0_DPCSTX_PLL_UPDATE_DATA

#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0

#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL



//DPCSTX0_DPCSTX_DEBUG_CONFIG

#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe

#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L



// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec

//RDPCSTX0_RDPCSTX_CNTL