Commit 7212b58d authored by Kiryl Shutsemau's avatar Kiryl Shutsemau Committed by Ingo Molnar
Browse files

x86/mm/64: Make 5-level paging support unconditional 



Both Intel and AMD CPUs support 5-level paging, which is expected to
become more widely adopted in the future. All major x86 Linux
distributions have the feature enabled.

Remove CONFIG_X86_5LEVEL and related #ifdeffery for it to make it more readable.

Suggested-by: default avatarBorislav Petkov <bp@alien8.de>
Signed-off-by: default avatarKirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Reviewed-by: default avatarArd Biesheuvel <ardb@kernel.org>
Reviewed-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20250516123306.3812286-4-kirill.shutemov@linux.intel.com
parent cba5d9b3

Documentation/arch/x86/cpuinfo.rst

+3 −5
Original line number Diff line number Diff line
@@ -173,10 +173,10 @@ For example, when an old kernel is running on new hardware. 
The kernel disabled support for it at compile-time

--------------------------------------------------



For example, if 5-level-paging is not enabled when building (i.e.,

CONFIG_X86_5LEVEL is not selected) the flag "la57" will not show up [#f1]_.

For example, if Linear Address Masking (LAM) is not enabled when building (i.e.,

CONFIG_ADDRESS_MASKING is not selected) the flag "lam" will not show up.

Even though the feature will still be detected via CPUID, the kernel disables

it by clearing via setup_clear_cpu_cap(X86_FEATURE_LA57).

it by clearing via setup_clear_cpu_cap(X86_FEATURE_LAM).



The feature is disabled at boot-time

------------------------------------
@@ -200,5 +200,3 @@ missing at runtime. For example, AVX flags will not show up if XSAVE feature 
is disabled since they depend on XSAVE feature. Another example would be broken

CPUs and them missing microcode patches. Due to that, the kernel decides not to

enable a feature.
 


.. [#f1] 5-level paging uses linear address of 57 bits.

Documentation/arch/x86/x86_64/5level-paging.rst

+0 −9
Original line number Diff line number Diff line
@@ -22,15 +22,6 @@ QEMU 2.9 and later support 5-level paging. 
Virtual memory layout for 5-level paging is described in

Documentation/arch/x86/x86_64/mm.rst





Enabling 5-level paging

=======================

CONFIG_X86_5LEVEL=y enables the feature.



Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.

In this case additional page table level -- p4d -- will be folded at

runtime.



User-space and large virtual address space

==========================================

On x86, 5-level paging enables 56-bit userspace virtual address space.

arch/x86/Kconfig

+1 −21
Original line number Diff line number Diff line
@@ -427,8 +427,7 @@ config DYNAMIC_PHYSICAL_MASK 


config PGTABLE_LEVELS

	int

	default 5 if X86_5LEVEL

	default 4 if X86_64

	default 5 if X86_64

	default 3 if X86_PAE

	default 2
@@ -1464,25 +1463,6 @@ config X86_PAE 
	  has the cost of more pagetable lookup overhead, and also

	  consumes more pagetable space per process.



config X86_5LEVEL

	bool "Enable 5-level page tables support"

	default y

	depends on X86_64

	help

	  5-level paging enables access to larger address space:

	  up to 128 PiB of virtual address space and 4 PiB of

	  physical address space.



	  It will be supported by future Intel CPUs.



	  A kernel with the option enabled can be booted on machines that

	  support 4- or 5-level paging.



	  See Documentation/arch/x86/x86_64/5level-paging.rst for more

	  information.



	  Say N if unsure.



config X86_DIRECT_GBPAGES

	def_bool y

	depends on X86_64

arch/x86/Kconfig.cpufeatures

+0 −4
Original line number Diff line number Diff line
@@ -132,10 +132,6 @@ config X86_DISABLED_FEATURE_OSPKE 
	def_bool y

	depends on !X86_INTEL_MEMORY_PROTECTION_KEYS



config X86_DISABLED_FEATURE_LA57

	def_bool y

	depends on !X86_5LEVEL



config X86_DISABLED_FEATURE_PTI

	def_bool y

	depends on !MITIGATION_PAGE_TABLE_ISOLATION

arch/x86/boot/compressed/pgtable_64.c

+2 −9
Original line number Diff line number Diff line
@@ -10,12 +10,10 @@ 
#define BIOS_START_MIN		0x20000U	/* 128K, less than this is insane */

#define BIOS_START_MAX		0x9f000U	/* 640K, absolute maximum */



#ifdef CONFIG_X86_5LEVEL

/* __pgtable_l5_enabled needs to be in .data to avoid being cleared along with .bss */

unsigned int __section(".data") __pgtable_l5_enabled;

unsigned int __section(".data") pgdir_shift = 39;

unsigned int __section(".data") ptrs_per_p4d = 1;

#endif



/* Buffer to preserve trampoline memory */

static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
@@ -114,18 +112,13 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable) 
	 * Check if LA57 is desired and supported.

	 *

	 * There are several parts to the check:

	 *   - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y

	 *   - if user asked to disable 5-level paging: no5lvl in cmdline

	 *   - if the machine supports 5-level paging:

	 *     + CPUID leaf 7 is supported

	 *     + the leaf has the feature bit set

	 *

	 * That's substitute for boot_cpu_has() in early boot code.

	 */

	if (IS_ENABLED(CONFIG_X86_5LEVEL) &&

			!cmdline_find_option_bool("no5lvl") &&

			native_cpuid_eax(0) >= 7 &&

			(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {

	if (!cmdline_find_option_bool("no5lvl") &&

	    native_cpuid_eax(0) >= 7 && (native_cpuid_ecx(7) & BIT(16))) {

		l5_required = true;



		/* Initialize variables for 5-level paging */