Commit 723c504b authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amd/pm: Use emit_clock_levels in SMUv7.0 



Move to emit_clock_levels from print_clock_levels

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c5842537

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c

+55 −32
Original line number Diff line number Diff line
@@ -4961,8 +4961,9 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, 
	return 0;

}



static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,

		enum pp_clock_type type, char *buf)

static int smu7_emit_clock_levels(struct pp_hwmgr *hwmgr,

				  enum pp_clock_type type, char *buf,

				  int *offset)

{

	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);

	struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
@@ -4971,7 +4972,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, 
	struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);

	struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);

	struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);

	int size = 0, ret = 0;

	int size = *offset, ret = 0;

	uint32_t i, now, clock, pcie_speed;



	switch (type) {
@@ -4987,8 +4988,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, 
		now = i;



		for (i = 0; i < sclk_table->count; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

					i, sclk_table->dpm_levels[i].value / 100,

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,

					      sclk_table->dpm_levels[i].value /

						      100,

					      (i == now) ? "*" : "");

		break;

	case PP_MCLK:
@@ -5003,8 +5005,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, 
		now = i;



		for (i = 0; i < mclk_table->count; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

					i, mclk_table->dpm_levels[i].value / 100,

			size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,

					      mclk_table->dpm_levels[i].value /

						      100,

					      (i == now) ? "*" : "");

		break;

	case PP_PCIE:
@@ -5017,40 +5020,57 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, 
		now = i;



		for (i = 0; i < pcie_table->count; i++)

			size += sprintf(buf + size, "%d: %s %s\n", i,

					(pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :

					(pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :

					(pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",

			size += sysfs_emit_at(

				buf, size, "%d: %s %s\n", i,

				(pcie_table->dpm_levels[i].value == 0) ?

					"2.5GT/s, x8" :

				(pcie_table->dpm_levels[i].value == 1) ?

					"5.0GT/s, x16" :

				(pcie_table->dpm_levels[i].value == 2) ?

					"8.0GT/s, x16" :

					"",

				(i == now) ? "*" : "");

		break;

	case OD_SCLK:

		if (hwmgr->od_enabled) {

			size += sprintf(buf + size, "%s:\n", "OD_SCLK");

			size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");

			for (i = 0; i < odn_sclk_table->num_of_pl; i++)

				size += sprintf(buf + size, "%d: %10uMHz %10umV\n",

					i, odn_sclk_table->entries[i].clock/100,

				size += sysfs_emit_at(

					buf, size, "%d: %10uMHz %10umV\n", i,

					odn_sclk_table->entries[i].clock / 100,

					odn_sclk_table->entries[i].vddc);

		}

		break;

	case OD_MCLK:

		if (hwmgr->od_enabled) {

			size += sprintf(buf + size, "%s:\n", "OD_MCLK");

			size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");

			for (i = 0; i < odn_mclk_table->num_of_pl; i++)

				size += sprintf(buf + size, "%d: %10uMHz %10umV\n",

					i, odn_mclk_table->entries[i].clock/100,

				size += sysfs_emit_at(

					buf, size, "%d: %10uMHz %10umV\n", i,

					odn_mclk_table->entries[i].clock / 100,

					odn_mclk_table->entries[i].vddc);

		}

		break;

	case OD_RANGE:

		if (hwmgr->od_enabled) {

			size += sprintf(buf + size, "%s:\n", "OD_RANGE");

			size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",

				data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,

				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);

			size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",

				data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,

				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);

			size += sprintf(buf + size, "VDDC: %7umV %11umV\n",

			size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");

			size += sysfs_emit_at(

				buf, size, "SCLK: %7uMHz %10uMHz\n",

				data->golden_dpm_table.sclk_table.dpm_levels[0]

						.value /

					100,

				hwmgr->platform_descriptor.overdriveLimit

						.engineClock /

					100);

			size += sysfs_emit_at(

				buf, size, "MCLK: %7uMHz %10uMHz\n",

				data->golden_dpm_table.mclk_table.dpm_levels[0]

						.value /

					100,

				hwmgr->platform_descriptor.overdriveLimit

						.memoryClock /

					100);

			size += sysfs_emit_at(buf, size, "VDDC: %7umV %11umV\n",

					      data->odn_dpm_table.min_vddc,

					      data->odn_dpm_table.max_vddc);

		}
@@ -5058,7 +5078,10 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, 
	default:

		break;

	}

	return size;



	*offset = size;



	return 0;

}



static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
@@ -5775,7 +5798,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = { 
	.set_fan_control_mode = smu7_set_fan_control_mode,

	.get_fan_control_mode = smu7_get_fan_control_mode,

	.force_clock_level = smu7_force_clock_level,

	.print_clock_levels = smu7_print_clock_levels,

	.emit_clock_levels = smu7_emit_clock_levels,

	.powergate_gfx = smu7_powergate_gfx,

	.get_sclk_od = smu7_get_sclk_od,

	.set_sclk_od = smu7_set_sclk_od,