Commit 72447125 authored by Jesse.Zhang's avatar Jesse.Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/mes12: implement detect and reset callback 



Implement support for the hung queue detect and reset
functionality.

v2: Always use AMDGPU_MES_SCHED_PIPE

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarJesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b28cfc83

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

+31 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 


#define MES_EOP_SIZE   2048



#define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 4



static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;
@@ -908,6 +910,32 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, 
			offsetof(union MESAPI__RESET, api_status));

}



static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes,

						  struct mes_detect_and_reset_queue_input *input)

{

	union MESAPI__RESET mes_reset_queue_pkt;



	memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));



	mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;

	mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET;

	mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;



	mes_reset_queue_pkt.queue_type =

		convert_to_mes_queue_type(input->queue_type);

	mes_reset_queue_pkt.doorbell_offset_addr =

		mes->hung_queue_db_array_gpu_addr;



	if (input->detect_only)

		mes_reset_queue_pkt.hang_detect_only = 1;

	else

		mes_reset_queue_pkt.hang_detect_then_reset = 1;



	return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE,

			&mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt),

			offsetof(union MESAPI__RESET, api_status));

}



static int mes_v12_inv_tlb_convert_hub_id(uint8_t id)

{

	/*
@@ -960,6 +988,7 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = { 
	.misc_op = mes_v12_0_misc_op,

	.reset_hw_queue = mes_v12_0_reset_hw_queue,

	.invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid,

	.detect_and_reset_hung_queues = mes_v12_0_detect_and_reset_hung_queues,

};



static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,
@@ -1865,6 +1894,8 @@ static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) 
	struct amdgpu_device *adev = ip_block->adev;

	int pipe, r;



	adev->mes.hung_queue_db_array_size =

		MES12_HUNG_DB_OFFSET_ARRAY_SIZE;

	for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {

		r = amdgpu_mes_init_microcode(adev, pipe);

		if (r)