Commit 72ae381b authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/rockchip' 

- Fix address translation unit programming (Damien Le Moal)

- Define ROCKCHIP_PCIE_AT_SIZE_ALIGN to replace magic 256 endpoint .align
  value (Damien Le Moal)

- When unmapping an endpoint window, compute the region index instead of
  searching for it, and verify that the address was mapped (Damien Le Moal)

- When mapping an endpoint window, verify that the address hasn't been
  mapped already (Damien Le Moal)

- Implement pci_epc_ops.align_addr() for rockchip-ep (Damien Le Moal)

- Fix MSI IRQ data mapping to observe the alignment constraint, which fixes
  intermittent page faults in memcpy_toio() and memcpy_fromio() (Damien Le
  Moal)

- Rename rockchip_pcie_parse_ep_dt() to rockchip_pcie_ep_get_resources()
  for consistency with similar DT interfaces (Damien Le Moal)

- Factor out memory allocations to tidy rockchip_pcie_ep_probe() (Damien Le
  Moal)

- Factor out MSI-X quirk to tidy rockchip_pcie_ep_probe() (Damien Le Moal)

- Skip the unnecessary link train in rockchip_pcie_ep_probe() and only in
  the endpoint start operation (Damien Le Moal)

- Implement pci_epc_ops.stop_link() to disable link training and controller
  configuration (Damien Le Moal)

- Attempt link training at 5 GT/s when both partners support it (Damien Le
  Moal)

- Add a handler for PERST# signal so we can detect host resets and start
  link training when exiting reset (Damien Le Moal)

* pci/controller/rockchip:
  PCI: rockchip-ep: Handle PERST# signal in EP mode
  PCI: rockchip-ep: Improve link training
  PCI: rockship-ep: Implement the pci_epc_ops::stop_link() operation
  PCI: rockchip-ep: Refactor endpoint link training enable
  PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() MSI-X hiding
  PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() memory allocations
  PCI: rockchip-ep: Rename rockchip_pcie_parse_ep_dt()
  PCI: rockchip-ep: Fix MSI IRQ data mapping
  PCI: rockchip-ep: Implement the pci_epc_ops::align_addr() operation
  PCI: rockchip-ep: Improve rockchip_pcie_ep_map_addr()
  PCI: rockchip-ep: Improve rockchip_pcie_ep_unmap_addr()
  PCI: rockchip-ep: Use a macro to define EP controller .align feature
  PCI: rockchip-ep: Fix address translation unit programming
parents f54ff407 a7137cbf

drivers/pci/controller/pcie-rockchip-ep.c

+357 −83
Original line number Diff line number Diff line
@@ -10,12 +10,16 @@ 


#include <linux/configfs.h>

#include <linux/delay.h>

#include <linux/gpio/consumer.h>

#include <linux/iopoll.h>

#include <linux/kernel.h>

#include <linux/irq.h>

#include <linux/of.h>

#include <linux/pci-epc.h>

#include <linux/platform_device.h>

#include <linux/pci-epf.h>

#include <linux/sizes.h>

#include <linux/workqueue.h>



#include "pcie-rockchip.h"
@@ -48,6 +52,10 @@ struct rockchip_pcie_ep { 
	u64			irq_pci_addr;

	u8			irq_pci_fn;

	u8			irq_pending;

	int			perst_irq;

	bool			perst_asserted;

	bool			link_up;

	struct delayed_work	link_training;

};



static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
@@ -63,15 +71,25 @@ static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip, 
			    ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));

}



static int rockchip_pcie_ep_ob_atu_num_bits(struct rockchip_pcie *rockchip,

					    u64 pci_addr, size_t size)

{

	int num_pass_bits = fls64(pci_addr ^ (pci_addr + size - 1));



	return clamp(num_pass_bits,

		     ROCKCHIP_PCIE_AT_MIN_NUM_BITS,

		     ROCKCHIP_PCIE_AT_MAX_NUM_BITS);

}



static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,

					 u32 r, u64 cpu_addr, u64 pci_addr,

					 size_t size)

{

	int num_pass_bits = fls64(size - 1);

	int num_pass_bits;

	u32 addr0, addr1, desc0;



	if (num_pass_bits < 8)

		num_pass_bits = 8;

	num_pass_bits = rockchip_pcie_ep_ob_atu_num_bits(rockchip,

							 pci_addr, size);



	addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |

		(lower_32_bits(pci_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
@@ -228,6 +246,28 @@ static inline u32 rockchip_ob_region(phys_addr_t addr) 
	return (addr >> ilog2(SZ_1M)) & 0x1f;

}



static u64 rockchip_pcie_ep_align_addr(struct pci_epc *epc, u64 pci_addr,

				       size_t *pci_size, size_t *addr_offset)

{

	struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);

	size_t size = *pci_size;

	u64 offset, mask;

	int num_bits;



	num_bits = rockchip_pcie_ep_ob_atu_num_bits(&ep->rockchip,

						    pci_addr, size);

	mask = (1ULL << num_bits) - 1;



	offset = pci_addr & mask;

	if (size + offset > SZ_1M)

		size = SZ_1M - offset;



	*pci_size = ALIGN(offset + size, ROCKCHIP_PCIE_AT_SIZE_ALIGN);

	*addr_offset = offset;



	return pci_addr & ~mask;

}



static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,

				     phys_addr_t addr, u64 pci_addr,

				     size_t size)
@@ -236,6 +276,9 @@ static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, 
	struct rockchip_pcie *pcie = &ep->rockchip;

	u32 r = rockchip_ob_region(addr);



	if (test_bit(r, &ep->ob_region_map))

		return -EBUSY;



	rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, addr, pci_addr, size);



	set_bit(r, &ep->ob_region_map);
@@ -249,13 +292,9 @@ static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn, 
{

	struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);

	struct rockchip_pcie *rockchip = &ep->rockchip;

	u32 r;



	for (r = 0; r < ep->max_regions; r++)

		if (ep->ob_addr[r] == addr)

			break;

	u32 r = rockchip_ob_region(addr);



	if (r == ep->max_regions)

	if (addr != ep->ob_addr[r] || !test_bit(r, &ep->ob_region_map))

		return;



	rockchip_pcie_clear_ep_ob_atu(rockchip, r);
@@ -351,9 +390,10 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, 
{

	struct rockchip_pcie *rockchip = &ep->rockchip;

	u32 flags, mme, data, data_mask;

	size_t irq_pci_size, offset;

	u64 irq_pci_addr;

	u8 msi_count;

	u64 pci_addr;

	u32 r;



	/* Check MSI enable bit */

	flags = rockchip_pcie_read(&ep->rockchip,
@@ -389,18 +429,21 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, 
				       PCI_MSI_ADDRESS_LO);



	/* Set the outbound region if needed. */

	if (unlikely(ep->irq_pci_addr != (pci_addr & PCIE_ADDR_MASK) ||

	irq_pci_size = ~PCIE_ADDR_MASK + 1;

	irq_pci_addr = rockchip_pcie_ep_align_addr(ep->epc,

						   pci_addr & PCIE_ADDR_MASK,

						   &irq_pci_size, &offset);

	if (unlikely(ep->irq_pci_addr != irq_pci_addr ||

		     ep->irq_pci_fn != fn)) {

		r = rockchip_ob_region(ep->irq_phys_addr);

		rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,

		rockchip_pcie_prog_ep_ob_atu(rockchip, fn,

					rockchip_ob_region(ep->irq_phys_addr),

					ep->irq_phys_addr,

					     pci_addr & PCIE_ADDR_MASK,

					     ~PCIE_ADDR_MASK + 1);

		ep->irq_pci_addr = (pci_addr & PCIE_ADDR_MASK);

					irq_pci_addr, irq_pci_size);

		ep->irq_pci_addr = irq_pci_addr;

		ep->irq_pci_fn = fn;

	}



	writew(data, ep->irq_cpu_addr + (pci_addr & ~PCIE_ADDR_MASK));

	writew(data, ep->irq_cpu_addr + offset + (pci_addr & ~PCIE_ADDR_MASK));

	return 0;

}
@@ -432,14 +475,222 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc) 


	rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);



	if (rockchip->perst_gpio)

		enable_irq(ep->perst_irq);



	/* Enable configuration and start link training */

	rockchip_pcie_write(rockchip,

			    PCIE_CLIENT_LINK_TRAIN_ENABLE |

			    PCIE_CLIENT_CONF_ENABLE,

			    PCIE_CLIENT_CONFIG);



	if (!rockchip->perst_gpio)

		schedule_delayed_work(&ep->link_training, 0);



	return 0;

}



static void rockchip_pcie_ep_stop(struct pci_epc *epc)

{

	struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);

	struct rockchip_pcie *rockchip = &ep->rockchip;



	if (rockchip->perst_gpio) {

		ep->perst_asserted = true;

		disable_irq(ep->perst_irq);

	}



	cancel_delayed_work_sync(&ep->link_training);



	/* Stop link training and disable configuration */

	rockchip_pcie_write(rockchip,

			    PCIE_CLIENT_CONF_DISABLE |

			    PCIE_CLIENT_LINK_TRAIN_DISABLE,

			    PCIE_CLIENT_CONFIG);

}



static void rockchip_pcie_ep_retrain_link(struct rockchip_pcie *rockchip)

{

	u32 status;



	status = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_LCS);

	status |= PCI_EXP_LNKCTL_RL;

	rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_LCS);

}



static bool rockchip_pcie_ep_link_up(struct rockchip_pcie *rockchip)

{

	u32 val = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS1);



	return PCIE_LINK_UP(val);

}



static void rockchip_pcie_ep_link_training(struct work_struct *work)

{

	struct rockchip_pcie_ep *ep =

		container_of(work, struct rockchip_pcie_ep, link_training.work);

	struct rockchip_pcie *rockchip = &ep->rockchip;

	struct device *dev = rockchip->dev;

	u32 val;

	int ret;



	/* Enable Gen1 training and wait for its completion */

	ret = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,

				 val, PCIE_LINK_TRAINING_DONE(val), 50,

				 LINK_TRAIN_TIMEOUT);

	if (ret)

		goto again;



	/* Make sure that the link is up */

	ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,

				 val, PCIE_LINK_UP(val), 50,

				 LINK_TRAIN_TIMEOUT);

	if (ret)

		goto again;



	/*

	 * Check the current speed: if gen2 speed was requested and we are not

	 * at gen2 speed yet, retrain again for gen2.

	 */

	val = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);

	if (!PCIE_LINK_IS_GEN2(val) && rockchip->link_gen == 2) {

		/* Enable retrain for gen2 */

		rockchip_pcie_ep_retrain_link(rockchip);

		readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,

				   val, PCIE_LINK_IS_GEN2(val), 50,

				   LINK_TRAIN_TIMEOUT);

	}



	/* Check again that the link is up */

	if (!rockchip_pcie_ep_link_up(rockchip))

		goto again;



	/*

	 * If PERST# was asserted while polling the link, do not notify

	 * the function.

	 */

	if (ep->perst_asserted)

		return;



	val = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS0);

	dev_info(dev,

		 "link up (negotiated speed: %sGT/s, width: x%lu)\n",

		 (val & PCIE_CLIENT_NEG_LINK_SPEED) ? "5" : "2.5",

		 ((val & PCIE_CLIENT_NEG_LINK_WIDTH_MASK) >>

		  PCIE_CLIENT_NEG_LINK_WIDTH_SHIFT) << 1);



	/* Notify the function */

	pci_epc_linkup(ep->epc);

	ep->link_up = true;



	return;



again:

	schedule_delayed_work(&ep->link_training, msecs_to_jiffies(5));

}



static void rockchip_pcie_ep_perst_assert(struct rockchip_pcie_ep *ep)

{

	struct rockchip_pcie *rockchip = &ep->rockchip;



	dev_dbg(rockchip->dev, "PERST# asserted, link down\n");



	if (ep->perst_asserted)

		return;



	ep->perst_asserted = true;



	cancel_delayed_work_sync(&ep->link_training);



	if (ep->link_up) {

		pci_epc_linkdown(ep->epc);

		ep->link_up = false;

	}

}



static void rockchip_pcie_ep_perst_deassert(struct rockchip_pcie_ep *ep)

{

	struct rockchip_pcie *rockchip = &ep->rockchip;



	dev_dbg(rockchip->dev, "PERST# de-asserted, starting link training\n");



	if (!ep->perst_asserted)

		return;



	ep->perst_asserted = false;



	/* Enable link re-training */

	rockchip_pcie_ep_retrain_link(rockchip);



	/* Start link training */

	schedule_delayed_work(&ep->link_training, 0);

}



static irqreturn_t rockchip_pcie_ep_perst_irq_thread(int irq, void *data)

{

	struct pci_epc *epc = data;

	struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);

	struct rockchip_pcie *rockchip = &ep->rockchip;

	u32 perst = gpiod_get_value(rockchip->perst_gpio);



	if (perst)

		rockchip_pcie_ep_perst_assert(ep);

	else

		rockchip_pcie_ep_perst_deassert(ep);



	irq_set_irq_type(ep->perst_irq,

			 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));



	return IRQ_HANDLED;

}



static int rockchip_pcie_ep_setup_irq(struct pci_epc *epc)

{

	struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);

	struct rockchip_pcie *rockchip = &ep->rockchip;

	struct device *dev = rockchip->dev;

	int ret;



	if (!rockchip->perst_gpio)

		return 0;



	/* PCIe reset interrupt */

	ep->perst_irq = gpiod_to_irq(rockchip->perst_gpio);

	if (ep->perst_irq < 0) {

		dev_err(dev,

			"failed to get IRQ for PERST# GPIO: %d\n",

			ep->perst_irq);



		return ep->perst_irq;

	}



	/*

	 * The perst_gpio is active low, so when it is inactive on start, it

	 * is high and will trigger the perst_irq handler. So treat this initial

	 * IRQ as a dummy one by faking the host asserting PERST#.

	 */

	ep->perst_asserted = true;

	irq_set_status_flags(ep->perst_irq, IRQ_NOAUTOEN);

	ret = devm_request_threaded_irq(dev, ep->perst_irq, NULL,

					rockchip_pcie_ep_perst_irq_thread,

					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,

					"pcie-ep-perst", epc);

	if (ret) {

		dev_err(dev,

			"failed to request IRQ for PERST# GPIO: %d\n",

			ret);



		return ret;

	}



	return 0;

}



static const struct pci_epc_features rockchip_pcie_epc_features = {

	.linkup_notifier = false,

	.linkup_notifier = true,

	.msi_capable = true,

	.msix_capable = false,

	.align = 256,

	.align = ROCKCHIP_PCIE_AT_SIZE_ALIGN,

};



static const struct pci_epc_features*
@@ -452,16 +703,18 @@ static const struct pci_epc_ops rockchip_pcie_epc_ops = { 
	.write_header	= rockchip_pcie_ep_write_header,

	.set_bar	= rockchip_pcie_ep_set_bar,

	.clear_bar	= rockchip_pcie_ep_clear_bar,

	.align_addr	= rockchip_pcie_ep_align_addr,

	.map_addr	= rockchip_pcie_ep_map_addr,

	.unmap_addr	= rockchip_pcie_ep_unmap_addr,

	.set_msi	= rockchip_pcie_ep_set_msi,

	.get_msi	= rockchip_pcie_ep_get_msi,

	.raise_irq	= rockchip_pcie_ep_raise_irq,

	.start		= rockchip_pcie_ep_start,

	.stop		= rockchip_pcie_ep_stop,

	.get_features	= rockchip_pcie_ep_get_features,

};



static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,

static int rockchip_pcie_ep_get_resources(struct rockchip_pcie *rockchip,

					  struct rockchip_pcie_ep *ep)

{

	struct device *dev = rockchip->dev;
@@ -496,91 +749,63 @@ static const struct of_device_id rockchip_pcie_ep_of_match[] = { 
	{},

};



static int rockchip_pcie_ep_probe(struct platform_device *pdev)

static int rockchip_pcie_ep_init_ob_mem(struct rockchip_pcie_ep *ep)

{

	struct device *dev = &pdev->dev;

	struct rockchip_pcie_ep *ep;

	struct rockchip_pcie *rockchip;

	struct pci_epc *epc;

	size_t max_regions;

	struct rockchip_pcie *rockchip = &ep->rockchip;

	struct device *dev = rockchip->dev;

	struct pci_epc_mem_window *windows = NULL;

	int err, i;

	u32 cfg_msi, cfg_msix_cp;



	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);

	if (!ep)

		return -ENOMEM;



	rockchip = &ep->rockchip;

	rockchip->is_rc = false;

	rockchip->dev = dev;



	epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);

	if (IS_ERR(epc)) {

		dev_err(dev, "failed to create epc device\n");

		return PTR_ERR(epc);

	}



	ep->epc = epc;

	epc_set_drvdata(epc, ep);



	err = rockchip_pcie_parse_ep_dt(rockchip, ep);

	if (err)

		return err;



	err = rockchip_pcie_enable_clocks(rockchip);

	if (err)

		return err;



	err = rockchip_pcie_init_port(rockchip);

	if (err)

		goto err_disable_clocks;



	/* Establish the link automatically */

	rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,

			    PCIE_CLIENT_CONFIG);



	max_regions = ep->max_regions;

	ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr),

	ep->ob_addr = devm_kcalloc(dev, ep->max_regions, sizeof(*ep->ob_addr),

				   GFP_KERNEL);



	if (!ep->ob_addr) {

		err = -ENOMEM;

		goto err_uninit_port;

	}



	/* Only enable function 0 by default */

	rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);

	if (!ep->ob_addr)

		return -ENOMEM;



	windows = devm_kcalloc(dev, ep->max_regions,

			       sizeof(struct pci_epc_mem_window), GFP_KERNEL);

	if (!windows) {

		err = -ENOMEM;

		goto err_uninit_port;

	}

	if (!windows)

		return -ENOMEM;



	for (i = 0; i < ep->max_regions; i++) {

		windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i);

		windows[i].size = SZ_1M;

		windows[i].page_size = SZ_1M;

	}

	err = pci_epc_multi_mem_init(epc, windows, ep->max_regions);

	err = pci_epc_multi_mem_init(ep->epc, windows, ep->max_regions);

	devm_kfree(dev, windows);



	if (err < 0) {

		dev_err(dev, "failed to initialize the memory space\n");

		goto err_uninit_port;

		return err;

	}



	ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,

	ep->irq_cpu_addr = pci_epc_mem_alloc_addr(ep->epc, &ep->irq_phys_addr,

						  SZ_1M);

	if (!ep->irq_cpu_addr) {

		dev_err(dev, "failed to reserve memory space for MSI\n");

		err = -ENOMEM;

		goto err_epc_mem_exit;

	}



	ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;



	return 0;



err_epc_mem_exit:

	pci_epc_mem_exit(ep->epc);



	return err;

}



static void rockchip_pcie_ep_exit_ob_mem(struct rockchip_pcie_ep *ep)

{

	pci_epc_mem_exit(ep->epc);

}



static void rockchip_pcie_ep_hide_broken_msix_cap(struct rockchip_pcie *rockchip)

{

	u32 cfg_msi, cfg_msix_cp;



	/*

	 * MSI-X is not supported but the controller still advertises the MSI-X

	 * capability by default, which can lead to the Root Complex side
@@ -603,19 +828,68 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) 


	rockchip_pcie_write(rockchip, cfg_msi,

			    PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG);

}



	rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE,

			    PCIE_CLIENT_CONFIG);

static int rockchip_pcie_ep_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct rockchip_pcie_ep *ep;

	struct rockchip_pcie *rockchip;

	struct pci_epc *epc;

	int err;



	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);

	if (!ep)

		return -ENOMEM;



	rockchip = &ep->rockchip;

	rockchip->is_rc = false;

	rockchip->dev = dev;

	INIT_DELAYED_WORK(&ep->link_training, rockchip_pcie_ep_link_training);



	epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);

	if (IS_ERR(epc)) {

		dev_err(dev, "failed to create EPC device\n");

		return PTR_ERR(epc);

	}



	ep->epc = epc;

	epc_set_drvdata(epc, ep);



	err = rockchip_pcie_ep_get_resources(rockchip, ep);

	if (err)

		return err;



	err = rockchip_pcie_ep_init_ob_mem(ep);

	if (err)

		return err;



	err = rockchip_pcie_enable_clocks(rockchip);

	if (err)

		goto err_exit_ob_mem;



	err = rockchip_pcie_init_port(rockchip);

	if (err)

		goto err_disable_clocks;



	rockchip_pcie_ep_hide_broken_msix_cap(rockchip);



	/* Only enable function 0 by default */

	rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);



	pci_epc_init_notify(epc);



	err = rockchip_pcie_ep_setup_irq(epc);

	if (err < 0)

		goto err_uninit_port;



	return 0;

err_epc_mem_exit:

	pci_epc_mem_exit(epc);

err_uninit_port:

	rockchip_pcie_deinit_phys(rockchip);

err_disable_clocks:

	rockchip_pcie_disable_clocks(rockchip);

err_exit_ob_mem:

	rockchip_pcie_ep_exit_ob_mem(ep);

	return err;

}

drivers/pci/controller/pcie-rockchip-host.c

+2 −2
Original line number Diff line number Diff line
@@ -294,7 +294,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) 
	int err, i = MAX_LANE_NUM;

	u32 status;



	gpiod_set_value_cansleep(rockchip->ep_gpio, 0);

	gpiod_set_value_cansleep(rockchip->perst_gpio, 0);



	err = rockchip_pcie_init_port(rockchip);

	if (err)
@@ -323,7 +323,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) 
			    PCIE_CLIENT_CONFIG);



	msleep(PCIE_T_PVPERL_MS);

	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);

	gpiod_set_value_cansleep(rockchip->perst_gpio, 1);



	msleep(PCIE_T_RRS_READY_MS);

drivers/pci/controller/pcie-rockchip.c

+12 −9
Original line number Diff line number Diff line
@@ -119,13 +119,15 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) 
		return PTR_ERR(rockchip->aclk_rst);

	}



	if (rockchip->is_rc) {

		rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep",

	if (rockchip->is_rc)

		rockchip->perst_gpio = devm_gpiod_get_optional(dev, "ep",

							       GPIOD_OUT_LOW);

		if (IS_ERR(rockchip->ep_gpio))

			return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio),

					     "failed to get ep GPIO\n");

	}

	else

		rockchip->perst_gpio = devm_gpiod_get_optional(dev, "reset",

							       GPIOD_IN);

	if (IS_ERR(rockchip->perst_gpio))

		return dev_err_probe(dev, PTR_ERR(rockchip->perst_gpio),

				     "failed to get PERST# GPIO\n");



	rockchip->aclk_pcie = devm_clk_get(dev, "aclk");

	if (IS_ERR(rockchip->aclk_pcie)) {
@@ -244,11 +246,12 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 
		rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,

				    PCIE_CLIENT_CONFIG);



	regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE |

	regs = PCIE_CLIENT_ARI_ENABLE |

	       PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);



	if (rockchip->is_rc)

		regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;

		regs |= PCIE_CLIENT_LINK_TRAIN_ENABLE |

			PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;

	else

		regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;

drivers/pci/controller/pcie-rockchip.h

+23 −1
Original line number Diff line number Diff line
@@ -26,12 +26,14 @@ 
#define MAX_LANE_NUM			4

#define MAX_REGION_LIMIT		32

#define MIN_EP_APERTURE			28

#define LINK_TRAIN_TIMEOUT		(500 * USEC_PER_MSEC)



#define PCIE_CLIENT_BASE		0x0

#define PCIE_CLIENT_CONFIG		(PCIE_CLIENT_BASE + 0x00)

#define   PCIE_CLIENT_CONF_ENABLE	  HIWORD_UPDATE_BIT(0x0001)

#define   PCIE_CLIENT_CONF_DISABLE       HIWORD_UPDATE(0x0001, 0)

#define   PCIE_CLIENT_LINK_TRAIN_ENABLE	  HIWORD_UPDATE_BIT(0x0002)

#define   PCIE_CLIENT_LINK_TRAIN_DISABLE  HIWORD_UPDATE(0x0002, 0)

#define   PCIE_CLIENT_ARI_ENABLE	  HIWORD_UPDATE_BIT(0x0008)

#define   PCIE_CLIENT_CONF_LANE_NUM(x)	  HIWORD_UPDATE(0x0030, ENCODE_LANES(x))

#define   PCIE_CLIENT_MODE_RC		  HIWORD_UPDATE_BIT(0x0040)
@@ -49,6 +51,10 @@ 
#define   PCIE_CLIENT_DEBUG_LTSSM_MASK		GENMASK(5, 0)

#define   PCIE_CLIENT_DEBUG_LTSSM_L1		0x18

#define   PCIE_CLIENT_DEBUG_LTSSM_L2		0x19

#define PCIE_CLIENT_BASIC_STATUS0	(PCIE_CLIENT_BASE + 0x44)

#define   PCIE_CLIENT_NEG_LINK_WIDTH_MASK	GENMASK(7, 6)

#define   PCIE_CLIENT_NEG_LINK_WIDTH_SHIFT	6

#define   PCIE_CLIENT_NEG_LINK_SPEED		BIT(5)

#define PCIE_CLIENT_BASIC_STATUS1	(PCIE_CLIENT_BASE + 0x48)

#define   PCIE_CLIENT_LINK_STATUS_UP		0x00300000

#define   PCIE_CLIENT_LINK_STATUS_MASK		0x00300000
@@ -86,6 +92,8 @@ 


#define PCIE_CORE_CTRL_MGMT_BASE	0x900000

#define PCIE_CORE_CTRL			(PCIE_CORE_CTRL_MGMT_BASE + 0x000)

#define   PCIE_CORE_PL_CONF_LS_MASK		0x00000001

#define   PCIE_CORE_PL_CONF_LS_READY		0x00000001

#define   PCIE_CORE_PL_CONF_SPEED_5G		0x00000008

#define   PCIE_CORE_PL_CONF_SPEED_MASK		0x00000018

#define   PCIE_CORE_PL_CONF_LANE_MASK		0x00000006
@@ -143,6 +151,7 @@ 
#define PCIE_RC_CONFIG_BASE		0xa00000

#define PCIE_EP_CONFIG_BASE		0xa00000

#define PCIE_EP_CONFIG_DID_VID		(PCIE_EP_CONFIG_BASE + 0x00)

#define PCIE_EP_CONFIG_LCS		(PCIE_EP_CONFIG_BASE + 0xd0)

#define PCIE_RC_CONFIG_RID_CCR		(PCIE_RC_CONFIG_BASE + 0x08)

#define PCIE_RC_CONFIG_DCR		(PCIE_RC_CONFIG_BASE + 0xc4)

#define   PCIE_RC_CONFIG_DCR_CSPL_SHIFT		18
@@ -154,6 +163,7 @@ 
#define PCIE_RC_CONFIG_LINK_CAP		(PCIE_RC_CONFIG_BASE + 0xcc)

#define   PCIE_RC_CONFIG_LINK_CAP_L0S		BIT(10)

#define PCIE_RC_CONFIG_LCS		(PCIE_RC_CONFIG_BASE + 0xd0)

#define PCIE_EP_CONFIG_LCS		(PCIE_EP_CONFIG_BASE + 0xd0)

#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)

#define PCIE_RC_CONFIG_THP_CAP		(PCIE_RC_CONFIG_BASE + 0x274)

#define   PCIE_RC_CONFIG_THP_CAP_NEXT_MASK	GENMASK(31, 20)
@@ -191,6 +201,8 @@ 
#define ROCKCHIP_VENDOR_ID			0x1d87

#define PCIE_LINK_IS_L2(x) \

	(((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2)

#define PCIE_LINK_TRAINING_DONE(x) \

	(((x) & PCIE_CORE_PL_CONF_LS_MASK) == PCIE_CORE_PL_CONF_LS_READY)

#define PCIE_LINK_UP(x) \

	(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)

#define PCIE_LINK_IS_GEN2(x) \
@@ -241,10 +253,20 @@ 
#define   ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK		GENMASK(15, 8)

#define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR				0x1

#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR		0x3



#define ROCKCHIP_PCIE_AT_MIN_NUM_BITS	8

#define ROCKCHIP_PCIE_AT_MAX_NUM_BITS	20

#define ROCKCHIP_PCIE_AT_SIZE_ALIGN	(1UL << ROCKCHIP_PCIE_AT_MIN_NUM_BITS)



#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) \

	(PCIE_EP_PF_CONFIG_REGS_BASE + (((fn) << 12) & GENMASK(19, 12)))

#define ROCKCHIP_PCIE_EP_VIRT_FUNC_BASE(fn) \

	(PCIE_EP_PF_CONFIG_REGS_BASE + 0x10000 + (((fn) << 12) & GENMASK(19, 12)))



#define ROCKCHIP_PCIE_AT_MIN_NUM_BITS  8

#define ROCKCHIP_PCIE_AT_MAX_NUM_BITS  20

#define ROCKCHIP_PCIE_AT_SIZE_ALIGN    (1UL << ROCKCHIP_PCIE_AT_MIN_NUM_BITS)



#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \

	(PCIE_CORE_AXI_CONF_BASE + 0x0828 + (fn) * 0x0040 + (bar) * 0x0008)

#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
@@ -307,7 +329,7 @@ struct rockchip_pcie { 
	struct	regulator *vpcie3v3; /* 3.3V power supply */

	struct	regulator *vpcie1v8; /* 1.8V power supply */

	struct	regulator *vpcie0v9; /* 0.9V power supply */

	struct	gpio_desc *ep_gpio;

	struct	gpio_desc *perst_gpio;

	u32	lanes;

	u8      lanes_map;

	int	link_gen;