Commit 72bea132 authored by Neil Armstrong's avatar Neil Armstrong Committed by Vinod Koul
Browse files

dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs 



The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.

Document the clock IDs to select the PIPE clock or the AUX clock,
also enforce a second clock-output-names and a #clock-cells value of 1
for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-1-3ec0a966d52f@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 7dcb8668

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

+24 −3
Original line number Diff line number Diff line
@@ -88,11 +88,11 @@ properties: 
          - description: offset of PCIe 4-lane configuration register

          - description: offset of configuration bit for this PHY



  "#clock-cells":

    const: 0

  "#clock-cells": true



  clock-output-names:

    maxItems: 1

    minItems: 1

    maxItems: 2



  "#phy-cells":

    const: 0
@@ -213,6 +213,27 @@ allOf: 
        reset-names:

          maxItems: 1



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sm8450-qmp-gen4x2-pcie-phy

              - qcom,sm8550-qmp-gen4x2-pcie-phy

              - qcom,sm8650-qmp-gen4x2-pcie-phy

    then:

      properties:

        clock-output-names:

          minItems: 2

        "#clock-cells":

          const: 1

    else:

      properties:

        clock-output-names:

          maxItems: 1

        "#clock-cells":

          const: 0



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

include/dt-bindings/phy/phy-qcom-qmp.h

+4 −0
Original line number Diff line number Diff line
@@ -17,4 +17,8 @@ 
#define QMP_USB43DP_USB3_PHY		0

#define QMP_USB43DP_DP_PHY		1



/* QMP PCIE PHYs */

#define QMP_PCIE_PIPE_CLK		0

#define QMP_PCIE_PHY_AUX_CLK		1



#endif /* _DT_BINDINGS_PHY_QMP */