Commit 72d47f32 authored by Max Merchel's avatar Max Merchel Committed by Frank Li
Browse files

ARM: dts: imx6ul/imx6ull: add boot phase properties 



dtschema/schemas/bootph.yaml describe various node usage during
boot phases with DT.

All SoCs require buses (aips and spba), clock, iomuxc and SOC access
during boot process.

Signed-off-by: default avatarMax Merchel <Max.Merchel@ew.tq-group.com>
Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
parent 24d209d1

arch/arm/boot/dts/nxp/imx/imx6ul.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ osc: clock-osc { 
		#clock-cells = <0>;

		clock-frequency = <24000000>;

		clock-output-names = "osc";

		bootph-pre-ram;

	};



	ipp_di0: clock-di0 {
@@ -143,6 +144,7 @@ soc: soc { 
		compatible = "simple-bus";

		interrupt-parent = <&gpc>;

		ranges;

		bootph-pre-ram;



		ocram: sram@900000 {

			compatible = "mmio-sram";
@@ -202,6 +204,7 @@ aips1: bus@2000000 { 
			#size-cells = <1>;

			reg = <0x02000000 0x100000>;

			ranges;

			bootph-pre-ram;



			spba-bus@2000000 {

				compatible = "fsl,spba-bus", "simple-bus";
@@ -209,6 +212,7 @@ spba-bus@2000000 { 
				#size-cells = <1>;

				reg = <0x02000000 0x40000>;

				ranges;

				bootph-pre-ram;



				ecspi1: spi@2008000 {

					#address-cells = <1>;
@@ -580,6 +584,7 @@ clks: clock-controller@20c4000 { 
				#clock-cells = <1>;

				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;

				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";

				bootph-pre-ram;

			};



			anatop: anatop@20c8000 {
@@ -745,6 +750,7 @@ power-domain@0 { 
			iomuxc: pinctrl@20e0000 {

				compatible = "fsl,imx6ul-iomuxc";

				reg = <0x020e0000 0x4000>;

				bootph-pre-ram;

			};



			gpr: iomuxc-gpr@20e4000 {
@@ -826,6 +832,7 @@ aips2: bus@2100000 { 
			#size-cells = <1>;

			reg = <0x02100000 0x100000>;

			ranges;

			bootph-pre-ram;



			crypto: crypto@2140000 {

				compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";

arch/arm/boot/dts/nxp/imx/imx6ull.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ aips3: bus@2200000 { 
			#size-cells = <1>;

			reg = <0x02200000 0x100000>;

			ranges;

			bootph-pre-ram;



			dcp: crypto@2280000 {

				compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp";