Commit 72d7a7fa authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
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drm/amd/display: Guard against setting dispclk low when active 



[Why]
We should never apply a minimum dispclk value while in prepare_bandwidth
or while displays are active. This is always an optimization for when
all displays are disabled.

[How]
Defer dispclk optimization until safe_to_lower = true and display_count
reaches 0.

Since 0 has a special value in this logic (ie. no dispclk required)
we also need adjust the logic that clamps it for the actual request
to PMFW.

Reviewed-by: default avatarGabe Teeger <gabe.teeger@amd.com>
Reviewed-by: default avatarLeo Chen <leo.chen@amd.com>
Reviewed-by: default avatarSyed Hassan <syed.hassan@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 07bc2dcb

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

+9 −4
Original line number Diff line number Diff line
@@ -467,14 +467,19 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, 
		update_dppclk = true;

	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&

	    (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {

		int requested_dispclk_khz = new_clocks->dispclk_khz;



		dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);



		if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)

			new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;

		/* Clamp the requested clock to PMFW based on their limit. */

		if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)

			requested_dispclk_khz = dc->debug.min_disp_clk_khz;



		dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz);

		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);



		dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);



		update_dispclk = true;