Commit 72fdf0bb authored by Alexander Usyskin's avatar Alexander Usyskin Committed by Greg Kroah-Hartman
Browse files

mei: csc: support controller with separate PCI device 



Intel PCI driver for chassis controller embedded in Intel graphics
devices.

An MEI device here called CSC can be embedded in discrete
Intel graphics devices having separate PCI device, to support a range
of chassis tasks such as graphics card firmware update and security tasks.

Reviewed-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarAlexander Usyskin <alexander.usyskin@intel.com>
Link: https://patch.msgid.link/20260201094358.1440593-7-alexander.usyskin@intel.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 60ca1597

drivers/misc/mei/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -58,6 +58,17 @@ config INTEL_MEI_GSC 
	  tasks such as graphics card firmware update and security

	  tasks.



config INTEL_MEI_CSC

	tristate "Intel MEI CSC embedded device"

	depends on INTEL_MEI_ME

	help

	  Intel PCI driver for the chassis controller embedded in Intel graphics devices.



	  An MEI device here called CSC can be embedded in discrete

	  Intel graphics devices, to support a range of chassis

	  tasks such as graphics card firmware update and security

	  tasks.



config INTEL_MEI_VSC_HW

	tristate "Intel visual sensing controller device transport driver"

	depends on ACPI && SPI

drivers/misc/mei/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -21,6 +21,9 @@ mei-me-objs += hw-me.o 
obj-$(CONFIG_INTEL_MEI_GSC) += mei-gsc.o

mei-gsc-objs := gsc-me.o



obj-$(CONFIG_INTEL_MEI_CSC) += mei-csc.o

mei-csc-objs := pci-csc.o



obj-$(CONFIG_INTEL_MEI_TXE) += mei-txe.o

mei-txe-objs := pci-txe.o

mei-txe-objs += hw-txe.o

drivers/misc/mei/hw-me-regs.h

+3 −0
Original line number Diff line number Diff line
@@ -124,6 +124,8 @@ 


#define PCI_DEVICE_ID_INTEL_MEI_NVL_S      0x6E68  /* Nova Lake Point S */



#define PCI_DEVICE_ID_INTEL_MEI_CRI        0x6766  /* Crescent Island */



/*

 * MEI HW Section

 */
@@ -134,6 +136,7 @@ 
#  define PCI_CFG_HFS_1_OPMODE_MSK 0xf0000 /* OP MODE Mask: SPS <= 4.0 */

#  define PCI_CFG_HFS_1_OPMODE_SPS 0xf0000 /* SPS SKU : SPS <= 4.0 */

#define PCI_CFG_HFS_2         0x48

#  define PCI_CFG_HFS_2_D3_BLOCK              BIT(7)

#  define PCI_CFG_HFS_2_PM_CMOFF_TO_CMX_ERROR 0x1000000 /* CMoff->CMx wake after an error */

#  define PCI_CFG_HFS_2_PM_CM_RESET_ERROR     0x5000000 /* CME reset due to exception */

#  define PCI_CFG_HFS_2_PM_EVENT_MASK         0xf000000

drivers/misc/mei/hw-me.c

+27 −0
Original line number Diff line number Diff line
@@ -224,6 +224,15 @@ static int mei_me_fw_status(struct mei_device *dev, 
	return 0;

}



static bool mei_csc_pg_blocked(struct mei_device *dev)

{

	struct mei_me_hw *hw = to_me_hw(dev);

	u32 reg = 0;



	hw->read_fws(dev, PCI_CFG_HFS_2, "PCI_CFG_HFS_2", &reg);

	return (reg & PCI_CFG_HFS_2_D3_BLOCK) == PCI_CFG_HFS_2_D3_BLOCK;

}



/**

 * mei_me_hw_config - configure hw dependent settings

 *
@@ -1206,6 +1215,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) 
				return ret;

		} else {

			hw->pg_state = MEI_PG_OFF;

			dev->pg_blocked = mei_csc_pg_blocked(dev);

		}

	}
@@ -1294,6 +1304,7 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) 
{

	struct mei_device *dev = (struct mei_device *) dev_id;

	struct list_head cmpl_list;

	bool pg_blocked;

	s32 slots;

	u32 hcsr;

	int rets = 0;
@@ -1351,6 +1362,14 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) 
		}

		goto end;

	}



	pg_blocked = mei_csc_pg_blocked(dev);

	if (pg_blocked && !dev->pg_blocked) /* PG block requested */

		pm_request_resume(&dev->dev);

	else if (!pg_blocked && dev->pg_blocked) /* PG block lifted */

		pm_request_autosuspend(&dev->dev);

	dev->pg_blocked = pg_blocked;



	/* check slots available for reading */

	slots = mei_count_full_read_slots(dev);

	while (slots > 0) {
@@ -1726,6 +1745,13 @@ static const struct mei_cfg mei_me_gscfi_cfg = { 
	MEI_CFG_FW_VER_SUPP,

};



/* Chassis System Controller Firmware Interface */

static const struct mei_cfg mei_me_csc_cfg = {

	MEI_CFG_TYPE_GSCFI,

	MEI_CFG_PCH8_HFS,

	MEI_CFG_FW_VER_SUPP,

};



/*

 * mei_cfg_list - A list of platform platform specific configurations.

 * Note: has to be synchronized with  enum mei_cfg_idx.
@@ -1748,6 +1774,7 @@ static const struct mei_cfg *const mei_cfg_list[] = { 
	[MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg,

	[MEI_ME_GSC_CFG] = &mei_me_gsc_cfg,

	[MEI_ME_GSCFI_CFG] = &mei_me_gscfi_cfg,

	[MEI_ME_CSC_CFG] = &mei_me_csc_cfg,

};



const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)

drivers/misc/mei/hw-me.h

+2 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw) 
 *                         SPS firmware exclusion.

 * @MEI_ME_GSC_CFG:        Graphics System Controller

 * @MEI_ME_GSCFI_CFG:      Graphics System Controller Firmware Interface

 * @MEI_ME_CSC_CFG:        Chassis System Controller Firmware Interface

 * @MEI_ME_NUM_CFG:        Upper Sentinel.

 */

enum mei_cfg_idx {
@@ -124,6 +125,7 @@ enum mei_cfg_idx { 
	MEI_ME_PCH15_SPS_CFG,

	MEI_ME_GSC_CFG,

	MEI_ME_GSCFI_CFG,

	MEI_ME_CSC_CFG,

	MEI_ME_NUM_CFG,

};