Commit 732b32da authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc: Remove core support for 40x 



Now that 40x platforms have gone, remove support
for 40x in the core of powerpc arch.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20240628121201.130802-4-mpe@ellerman.id.au
parent e939da89

arch/powerpc/include/asm/cputable.h

+0 −7
Original line number Diff line number Diff line
@@ -353,7 +353,6 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE  | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON)

#define CPU_FTRS_8XX	(CPU_FTR_NOEXECUTE)

#define CPU_FTRS_40X	(CPU_FTR_NOEXECUTE)

#define CPU_FTRS_44X	(CPU_FTR_NOEXECUTE)

#define CPU_FTRS_440x6	(CPU_FTR_NOEXECUTE | \

	    CPU_FTR_INDEXED_DCR)
@@ -507,9 +506,6 @@ enum { 
#ifdef CONFIG_PPC_8xx

	    CPU_FTRS_8XX |

#endif

#ifdef CONFIG_40x

	    CPU_FTRS_40X |

#endif

#ifdef CONFIG_PPC_47x

	    CPU_FTRS_47X | CPU_FTR_476_DD2 |

#elif defined(CONFIG_44x)
@@ -582,9 +578,6 @@ enum { 
#ifdef CONFIG_PPC_8xx

	    CPU_FTRS_8XX &

#endif

#ifdef CONFIG_40x

	    CPU_FTRS_40X &

#endif

#ifdef CONFIG_PPC_47x

	    CPU_FTRS_47X &

#elif defined(CONFIG_44x)

arch/powerpc/include/asm/mmu.h

+0 −7
Original line number Diff line number Diff line
@@ -16,7 +16,6 @@ 
 */

#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)

#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)

#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)

#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)

#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)

#define MMU_FTR_TYPE_47x		ASM_CONST(0x00000020)
@@ -153,9 +152,6 @@ enum { 
#ifdef CONFIG_PPC_8xx

		MMU_FTR_TYPE_8xx |

#endif

#ifdef CONFIG_40x

		MMU_FTR_TYPE_40x |

#endif

#ifdef CONFIG_PPC_47x

		MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL |

#elif defined(CONFIG_44x)
@@ -202,9 +198,6 @@ enum { 
#ifdef CONFIG_PPC_8xx

#define MMU_FTRS_ALWAYS		MMU_FTR_TYPE_8xx

#endif

#ifdef CONFIG_40x

#define MMU_FTRS_ALWAYS		MMU_FTR_TYPE_40x

#endif

#ifdef CONFIG_PPC_47x

#define MMU_FTRS_ALWAYS		MMU_FTR_TYPE_47x

#elif defined(CONFIG_44x)

arch/powerpc/include/asm/nohash/32/mmu-40x.h

deleted100644 → 0
+0 −68
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_POWERPC_MMU_40X_H_

#define _ASM_POWERPC_MMU_40X_H_



/*

 * PPC40x support

 */



#define PPC40X_TLB_SIZE 64



/*

 * TLB entries are defined by a "high" tag portion and a "low" data

 * portion.  On all architectures, the data portion is 32-bits.

 *

 * TLB entries are managed entirely under software control by reading,

 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx

 * instructions.

 */



#define	TLB_LO          1

#define	TLB_HI          0



#define	TLB_DATA        TLB_LO

#define	TLB_TAG         TLB_HI



/* Tag portion */



#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */

#define TLB_PAGESZ_MASK 0x00000380

#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)

#define   PAGESZ_1K		0

#define   PAGESZ_4K             1

#define   PAGESZ_16K            2

#define   PAGESZ_64K            3

#define   PAGESZ_256K           4

#define   PAGESZ_1M             5

#define   PAGESZ_4M             6

#define   PAGESZ_16M            7

#define TLB_VALID       0x00000040      /* Entry is valid */



/* Data portion */



#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */

#define TLB_PERM_MASK   0x00000300

#define TLB_EX          0x00000200      /* Instruction execution allowed */

#define TLB_WR          0x00000100      /* Writes permitted */

#define TLB_ZSEL_MASK   0x000000F0

#define TLB_ZSEL(x)     (((x) & 0xF) << 4)

#define TLB_ATTR_MASK   0x0000000F

#define TLB_W           0x00000008      /* Caching is write-through */

#define TLB_I           0x00000004      /* Caching is inhibited */

#define TLB_M           0x00000002      /* Memory is coherent */

#define TLB_G           0x00000001      /* Memory is guarded from prefetch */



#ifndef __ASSEMBLY__



typedef struct {

	unsigned int	id;

	unsigned int	active;

	void __user	*vdso;

} mm_context_t;



#endif /* !__ASSEMBLY__ */



#define mmu_virtual_psize	MMU_PAGE_4K

#define mmu_linear_psize	MMU_PAGE_256M



#endif /* _ASM_POWERPC_MMU_40X_H_ */

arch/powerpc/include/asm/nohash/32/pgtable.h

+1 −3
Original line number Diff line number Diff line
@@ -118,9 +118,7 @@ 
 * (hardware-defined) PowerPC PTE as closely as possible.

 */



#if defined(CONFIG_40x)

#include <asm/nohash/32/pte-40x.h>

#elif defined(CONFIG_44x)

#if defined(CONFIG_44x)

#include <asm/nohash/32/pte-44x.h>

#elif defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT)

#include <asm/nohash/pte-e500.h>

arch/powerpc/include/asm/nohash/32/pte-40x.h

deleted100644 → 0
+0 −73
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_POWERPC_NOHASH_32_PTE_40x_H

#define _ASM_POWERPC_NOHASH_32_PTE_40x_H

#ifdef __KERNEL__



/*

 * At present, all PowerPC 400-class processors share a similar TLB

 * architecture. The instruction and data sides share a unified,

 * 64-entry, fully-associative TLB which is maintained totally under

 * software control. In addition, the instruction side has a

 * hardware-managed, 4-entry, fully-associative TLB which serves as a

 * first level to the shared TLB. These two TLBs are known as the UTLB

 * and ITLB, respectively (see "mmu.h" for definitions).

 *

 * There are several potential gotchas here.  The 40x hardware TLBLO

 * field looks like this:

 *

 * 0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31

 * RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G

 *

 * Where possible we make the Linux PTE bits match up with this

 *

 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can

 *   support down to 1k pages), this is done in the TLBMiss exception

 *   handler.

 * - We use only zones 0 (for kernel pages) and 1 (for user pages)

 *   of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB

 *   miss handler.  Bit 27 is PAGE_USER, thus selecting the correct

 *   zone.

 * - PRESENT *must* be in the bottom two bits because swap PTEs

 *   use the top 30 bits.  Because 40x doesn't support SMP anyway, M is

 *   irrelevant so we borrow it for PAGE_PRESENT.  Bit 30

 *   is cleared in the TLB miss handler before the TLB entry is loaded.

 * - All other bits of the PTE are loaded into TLBLO without

 *   modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for

 *   software PTE bits.  We actually use bits 21, 24, 25, and

 *   30 respectively for the software bits: ACCESSED, DIRTY, RW, and

 *   PRESENT.

 */



#define	_PAGE_GUARDED	0x001	/* G: page is guarded from prefetch */

#define _PAGE_PRESENT	0x002	/* software: PTE contains a translation */

#define	_PAGE_NO_CACHE	0x004	/* I: caching is inhibited */

#define	_PAGE_WRITETHRU	0x008	/* W: caching is write-through */

#define	_PAGE_READ	0x010	/* software: read permission */

#define	_PAGE_SPECIAL	0x020	/* software: Special page */

#define	_PAGE_DIRTY	0x080	/* software: dirty page */

#define _PAGE_WRITE	0x100	/* hardware: WR, anded with dirty in exception */

#define _PAGE_EXEC	0x200	/* hardware: EX permission */

#define _PAGE_ACCESSED	0x400	/* software: R: page referenced */



/* No page size encoding in the linux PTE */

#define _PAGE_PSIZE		0



/* cache related flags non existing on 40x */

#define _PAGE_COHERENT	0



#define _PMD_PRESENT	0x400	/* PMD points to page of PTEs */

#define _PMD_PRESENT_MASK	_PMD_PRESENT

#define _PMD_BAD	0x802

#define _PMD_SIZE_4M	0x0c0

#define _PMD_SIZE_16M	0x0e0

#define _PMD_USER	0



#define _PTE_NONE_MASK	0



#define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED)

#define _PAGE_BASE	(_PAGE_BASE_NC)



#include <asm/pgtable-masks.h>



#endif /* __KERNEL__ */

#endif /*  _ASM_POWERPC_NOHASH_32_PTE_40x_H */