Commit 738d7d03 authored by Dhananjay Ugwekar's avatar Dhananjay Ugwekar Committed by Mario Limonciello
Browse files

cpufreq/amd-pstate: Fix the scaling_max_freq setting on shared memory CPPC systems 



On shared memory CPPC systems, with amd_pstate=active mode, the change
in scaling_max_freq doesn't get written to the shared memory
region. Due to this, the writes to the scaling_max_freq sysfs file
don't take effect. Fix this by propagating the scaling_max_freq
changes to the shared memory region.

Fixes: ffa5096a ("cpufreq: amd-pstate: implement Pstate EPP support for the AMD processors")
Reported-by: default avatarDavid Arcari <darcari@redhat.com>
Signed-off-by: default avatarDhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Reviewed-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20240702081413.5688-3-Dhananjay.Ugwekar@amd.com


Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
parent f21ab5ed

drivers/cpufreq/amd-pstate.c

+23 −20
Original line number Diff line number Diff line
@@ -239,6 +239,26 @@ static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata) 
	return index;

}



static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,

			       u32 des_perf, u32 max_perf, bool fast_switch)

{

	if (fast_switch)

		wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached));

	else

		wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,

			      READ_ONCE(cpudata->cppc_req_cached));

}



DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);



static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,

					  u32 min_perf, u32 des_perf,

					  u32 max_perf, bool fast_switch)

{

	static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf,

					    max_perf, fast_switch);

}



static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)

{

	int ret;
@@ -255,6 +275,9 @@ static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) 
		if (!ret)

			cpudata->epp_cached = epp;

	} else {

		amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U,

					     cpudata->max_limit_perf, false);



		perf_ctrls.energy_perf = epp;

		ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);

		if (ret) {
@@ -442,16 +465,6 @@ static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) 
	return static_call(amd_pstate_init_perf)(cpudata);

}



static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,

			       u32 des_perf, u32 max_perf, bool fast_switch)

{

	if (fast_switch)

		wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached));

	else

		wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,

			      READ_ONCE(cpudata->cppc_req_cached));

}



static void cppc_update_perf(struct amd_cpudata *cpudata,

			     u32 min_perf, u32 des_perf,

			     u32 max_perf, bool fast_switch)
@@ -465,16 +478,6 @@ static void cppc_update_perf(struct amd_cpudata *cpudata, 
	cppc_set_perf(cpudata->cpu, &perf_ctrls);

}



DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);



static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,

					  u32 min_perf, u32 des_perf,

					  u32 max_perf, bool fast_switch)

{

	static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf,

					    max_perf, fast_switch);

}



static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)

{

	u64 aperf, mperf, tsc;