Unverified Commit 739058a9 authored by Moudy Ho's avatar Moudy Ho Committed by AngeloGioacchino Del Regno
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dt-bindings: display: mediatek: split: add compatible for MT8195



Add compatible string and GCE property for MT8195 SPLIT, of
which is operated by MDP3.

Signed-off-by: default avatarMoudy Ho <moudy.ho@mediatek.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent fe49f432
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+27 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ properties:
    oneOf:
      - enum:
          - mediatek,mt8173-disp-split
          - mediatek,mt8195-mdp3-split
      - items:
          - const: mediatek,mt6795-disp-split
          - const: mediatek,mt8173-disp-split
@@ -38,6 +39,21 @@ properties:
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  mediatek,gce-client-reg:
    description:
      The register of display function block to be set by gce. There are 4 arguments,
      such as gce node, subsys id, offset and register size. The subsys id that is
      mapping to the register of display function blocks is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    maxItems: 1

  clocks:
    items:
      - description: SPLIT Clock
@@ -48,6 +64,17 @@ required:
  - power-domains
  - clocks

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt8195-mdp3-split

    then:
      required:
        - mediatek,gce-client-reg

additionalProperties: false

examples: