Commit 73b46467 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Vinod Koul
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dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G 



The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
additional PHY modes like QSGMII. Add a compatible for it.

Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.

Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230315092408.1722114-1-s-vadapalli@ti.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 57c0e136

Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml

+4 −0
Original line number Diff line number Diff line
@@ -55,6 +55,7 @@ properties: 
      - ti,am654-phy-gmii-sel

      - ti,j7200-cpsw5g-phy-gmii-sel

      - ti,j721e-cpsw9g-phy-gmii-sel

      - ti,j784s4-cpsw9g-phy-gmii-sel



  reg:

    maxItems: 1
@@ -87,6 +88,7 @@ allOf: 
              - ti,am654-phy-gmii-sel

              - ti,j7200-cpsw5g-phy-gmii-sel

              - ti,j721e-cpsw9g-phy-gmii-sel

              - ti,j784s4-cpsw9g-phy-gmii-sel

    then:

      properties:

        '#phy-cells':
@@ -113,6 +115,7 @@ allOf: 
          contains:

            enum:

              - ti,j721e-cpsw9g-phy-gmii-sel

              - ti,j784s4-cpsw9g-phy-gmii-sel

    then:

      properties:

        ti,qsgmii-main-ports:
@@ -130,6 +133,7 @@ allOf: 
              enum:

                - ti,j7200-cpsw5g-phy-gmii-sel

                - ti,j721e-cpsw9g-phy-gmii-sel

                - ti,j784s4-cpsw9g-phy-gmii-sel

    then:

      properties:

        ti,qsgmii-main-ports: false