Commit 73e6ffa3 authored by Vimlesh Kumar's avatar Vimlesh Kumar Committed by Paolo Abeni
Browse files

octeon_ep: disable per ring interrupts 



Disable the MSI-X per ring interrupt for every PF ring when PF
netdev goes down.

Fixes: 1f2c2d0c ("octeon_ep: add hardware configuration APIs")
Signed-off-by: default avatarSathesh Edara <sedara@marvell.com>
Signed-off-by: default avatarShinas Rasheed <srasheed@marvell.com>
Signed-off-by: default avatarVimlesh Kumar <vimleshk@marvell.com>
Link: https://patch.msgid.link/20260206111510.1045092-2-vimleshk@marvell.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 36bd7d5d

drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c

+15 −3
Original line number Diff line number Diff line
@@ -696,14 +696,26 @@ static void octep_enable_interrupts_cn93_pf(struct octep_device *oct) 
/* Disable all interrupts */

static void octep_disable_interrupts_cn93_pf(struct octep_device *oct)

{

	u64 intr_mask = 0ULL;

	u64 reg_val, intr_mask = 0ULL;

	int srn, num_rings, i;



	srn = CFG_GET_PORTS_PF_SRN(oct->conf);

	num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);



	for (i = 0; i < num_rings; i++)

		intr_mask |= (0x1ULL << (srn + i));

	for (i = 0; i < num_rings; i++) {

		intr_mask |= BIT_ULL(srn + i);

		reg_val = octep_read_csr64(oct,

					   CN93_SDP_R_IN_INT_LEVELS(srn + i));

		reg_val &= ~CN93_INT_ENA_BIT;

		octep_write_csr64(oct,

				  CN93_SDP_R_IN_INT_LEVELS(srn + i), reg_val);



		reg_val = octep_read_csr64(oct,

					   CN93_SDP_R_OUT_INT_LEVELS(srn + i));

		reg_val &= ~CN93_INT_ENA_BIT;

		octep_write_csr64(oct,

				  CN93_SDP_R_OUT_INT_LEVELS(srn + i), reg_val);

	}



	octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask);

	octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask);

drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

+15 −3
Original line number Diff line number Diff line
@@ -720,14 +720,26 @@ static void octep_enable_interrupts_cnxk_pf(struct octep_device *oct) 
/* Disable all interrupts */

static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct)

{

	u64 intr_mask = 0ULL;

	u64 reg_val, intr_mask = 0ULL;

	int srn, num_rings, i;



	srn = CFG_GET_PORTS_PF_SRN(oct->conf);

	num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);



	for (i = 0; i < num_rings; i++)

		intr_mask |= (0x1ULL << (srn + i));

	for (i = 0; i < num_rings; i++) {

		intr_mask |= BIT_ULL(srn + i);

		reg_val = octep_read_csr64(oct,

					   CNXK_SDP_R_IN_INT_LEVELS(srn + i));

		reg_val &= ~CNXK_INT_ENA_BIT;

		octep_write_csr64(oct,

				  CNXK_SDP_R_IN_INT_LEVELS(srn + i), reg_val);



		reg_val = octep_read_csr64(oct,

					   CNXK_SDP_R_OUT_INT_LEVELS(srn + i));

		reg_val &= ~CNXK_INT_ENA_BIT;

		octep_write_csr64(oct,

				  CNXK_SDP_R_OUT_INT_LEVELS(srn + i), reg_val);

	}



	octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask);

	octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask);

drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h

+1 −0
Original line number Diff line number Diff line
@@ -386,5 +386,6 @@ 
#define CN93_PEM_BAR4_INDEX            7

#define CN93_PEM_BAR4_INDEX_SIZE       0x400000ULL

#define CN93_PEM_BAR4_INDEX_OFFSET     (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE)

#define CN93_INT_ENA_BIT	BIT_ULL(62)



#endif /* _OCTEP_REGS_CN9K_PF_H_ */

drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h

+1 −0
Original line number Diff line number Diff line
@@ -412,5 +412,6 @@ 
#define CNXK_PEM_BAR4_INDEX		7

#define CNXK_PEM_BAR4_INDEX_SIZE	0x400000ULL

#define CNXK_PEM_BAR4_INDEX_OFFSET	(CNXK_PEM_BAR4_INDEX * CNXK_PEM_BAR4_INDEX_SIZE)

#define CNXK_INT_ENA_BIT	BIT_ULL(62)



#endif /* _OCTEP_REGS_CNXK_PF_H_ */