Commit 7407f2e5 authored by Niranjana Vishwanathapura's avatar Niranjana Vishwanathapura Committed by Rodrigo Vivi
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drm/xe/pvc: Force even num engines to use 64B 



Wa_16017236439 requires that we update BCS_SWCTRL
(via indirect context batch buffer) to set 64B
transfers when running on an even-numbered BCS
engine and 256B on an odd-numbered BCS engine.

v2: Move WA from engine_was[] to lrc_was[]

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: default avatarNiranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 25063811

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ 
#define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)



#define BCS_SWCTRL(base)			XE_REG((base) + 0x200, XE_REG_OPTION_MASKED)

#define   BCS_SWCTRL_DISABLE_256B		REG_BIT(2)



/* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */

#define BLIT_CCTL(base)				XE_REG((base) + 0x204)

drivers/gpu/drm/xe/xe_wa.c

+10 −0
Original line number Diff line number Diff line
@@ -604,6 +604,16 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE))

	},



	/* PVC */



	{ XE_RTP_NAME("16017236439"),

	  XE_RTP_RULES(PLATFORM(PVC), ENGINE_CLASS(COPY),

		       FUNC(xe_rtp_match_even_instance)),

	  XE_RTP_ACTIONS(SET(BCS_SWCTRL(0),

			     BCS_SWCTRL_DISABLE_256B,

			     XE_RTP_ACTION_FLAG(ENGINE_BASE))),

	},



	/* Xe_LPG */

	{ XE_RTP_NAME("18019271663"),

	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),