Commit 745d755b authored by Taniya Das's avatar Taniya Das Committed by Bjorn Andersson
Browse files

clk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLs 



Add clock ops for Taycan PLL, add the register offsets for supporting
the PLL.

Signed-off-by: default avatarMelody Olvera <quic_molvera@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-4-1a8f31a53a86@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent c035a9e2

drivers/clk/qcom/clk-alpha-pll.c

+14 −0
Original line number Diff line number Diff line
@@ -197,6 +197,20 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_TEST_CTL_U1] = 0x34,

		[PLL_OFF_TEST_CTL_U2] = 0x38,

	},

	[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] = {

		[PLL_OFF_OPMODE] = 0x04,

		[PLL_OFF_STATE] = 0x08,

		[PLL_OFF_STATUS] = 0x0c,

		[PLL_OFF_L_VAL] = 0x10,

		[PLL_OFF_ALPHA_VAL] = 0x14,

		[PLL_OFF_USER_CTL] = 0x18,

		[PLL_OFF_USER_CTL_U] = 0x1c,

		[PLL_OFF_CONFIG_CTL] = 0x20,

		[PLL_OFF_CONFIG_CTL_U] = 0x24,

		[PLL_OFF_CONFIG_CTL_U1] = 0x28,

		[PLL_OFF_TEST_CTL] = 0x2c,

		[PLL_OFF_TEST_CTL_U] = 0x30,

	},

	[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {

		[PLL_OFF_OPMODE] = 0x04,

		[PLL_OFF_STATUS] = 0x0c,

drivers/clk/qcom/clk-alpha-pll.h

+7 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ enum { 
	CLK_ALPHA_PLL_TYPE_ZONDA_OLE,

	CLK_ALPHA_PLL_TYPE_LUCID_EVO,

	CLK_ALPHA_PLL_TYPE_LUCID_OLE,

	CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,

	CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,

	CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,

	CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
@@ -185,12 +186,15 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops; 
#define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops



extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;

#define clk_alpha_pll_taycan_elu_ops clk_alpha_pll_lucid_evo_ops

extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;

#define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops

extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;

#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops

#define clk_alpha_pll_fixed_taycan_elu_ops clk_alpha_pll_fixed_lucid_evo_ops

extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;

#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops

#define clk_alpha_pll_postdiv_taycan_elu_ops clk_alpha_pll_postdiv_lucid_evo_ops



extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;

#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
@@ -218,6 +222,9 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma 
				 const struct alpha_pll_config *config);

void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				 const struct alpha_pll_config *config);

#define clk_taycan_elu_pll_configure(pll, regmap, config) \

	clk_lucid_evo_pll_configure(pll, regmap, config)



void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				  const struct alpha_pll_config *config);

void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,