Commit 7479d267 authored by Jarkko Nikula's avatar Jarkko Nikula Committed by Alexandre Belloni
Browse files

i3c: mipi-i3c-hci: Change name of INTR_STATUS bit 11 



INTR_STATUS bit 11 INTR_HC_RESET_CANCEL was probably projected for the
MIPI I3C HCI specification version 2 but was not ever implemented.

This bit is first time specified in the v1.2 as HC_SEQ_CANCEL_STAT
"Host Controller Cancelled Transaction Sequence". Update the definition
and debug print of it accordingly.

While at it, change DBG() print to dev_dbg().

Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarJarkko Nikula <jarkko.nikula@linux.intel.com>
Link: https://lore.kernel.org/r/20250409140401.299251-4-jarkko.nikula@linux.intel.com


Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
parent a7035a8e

drivers/i3c/master/mipi-i3c-hci/core.c

+5 −4
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ 
#define INTR_SIGNAL_ENABLE		0x28

#define INTR_FORCE			0x2c

#define INTR_HC_CMD_SEQ_UFLOW_STAT	BIT(12)	/* Cmd Sequence Underflow */

#define INTR_HC_RESET_CANCEL		BIT(11)	/* HC Cancelled Reset */

#define INTR_HC_SEQ_CANCEL		BIT(11)	/* HC Cancelled Transaction Sequence */

#define INTR_HC_INTERNAL_ERR		BIT(10)	/* HC Internal Error */



#define DAT_SECTION			0x30	/* Device Address Table */
@@ -596,9 +596,10 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id) 
	if (val)

		result = IRQ_HANDLED;



	if (val & INTR_HC_RESET_CANCEL) {

		DBG("cancelled reset");

		val &= ~INTR_HC_RESET_CANCEL;

	if (val & INTR_HC_SEQ_CANCEL) {

		dev_dbg(&hci->master.dev,

			"Host Controller Cancelled Transaction Sequence\n");

		val &= ~INTR_HC_SEQ_CANCEL;

	}

	if (val & INTR_HC_INTERNAL_ERR) {

		dev_err(&hci->master.dev, "Host Controller Internal Error\n");