Commit 7487986c authored by Anson Huang's avatar Anson Huang Committed by Abel Vesa
Browse files

clk: imx: scu: Only save DC SS clock using non-cached clock rate 



Display sub-system has special clock settings in SCFW, the
bypassed clock is used instead of PLL in Linux kernel clock
tree, so when saving clock rate, need to save non-cached clock
rate for Display sub-system's bypass clocks, and other clocks
still use the cached clock rate which is with runtime PM ON.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@nxp.com>
Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
parent a43f6e8a

drivers/clk/imx/clk-scu.c

+8 −1
Original line number Diff line number Diff line
@@ -547,6 +547,13 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev) 
	    (rsrc_id == IMX_SC_R_A72))

		return 0;



	/* DC SS needs to handle bypass clock using non-cached clock rate */

	if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||

		clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||

		clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||

		clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)

		clk->rate = clk_scu_recalc_rate(&clk->hw, 0);

	else

		clk->rate = clk_hw_get_rate(&clk->hw);

	clk->is_enabled = clk_hw_is_enabled(&clk->hw);