Commit 748b0aeb authored by Daniel Golle's avatar Daniel Golle Committed by Jakub Kicinski
Browse files

net: dsa: lantiq_gswip: replace *_mask() functions with regmap API 



Use coccinelle to replace all uses of *_mask() with an equivalent call
to regmap_write_bits().

// Replace gswip_switch_mask with regmap_write_bits
@@
expression priv, clear, set, offset;
@@
- gswip_switch_mask(priv, clear, set, offset)
+ regmap_write_bits(priv->gswip, offset, clear | set, set)

// Replace gswip_mdio_mask with regmap_write_bits
@@
expression priv, clear, set, offset;
@@
- gswip_mdio_mask(priv, clear, set, offset)
+ regmap_write_bits(priv->mdio, offset, clear | set, set)

// Replace gswip_mii_mask with regmap_write_bits
@@
expression priv, clear, set, offset;
@@
- gswip_mii_mask(priv, clear, set, offset)
+ regmap_write_bits(priv->mii, offset, clear | set, set)

Remove the new unused *_mask() functions.
This naive approach will be further optmized manually in the next commit.

Signed-off-by: default avatarDaniel Golle <daniel@makrotopia.org>
Acked-by; Hauke Mehrtens <hauke@hauke-m.de>:
Acked-by; Hauke Mehrtens <hauke@hauke-m.de>:
Link: https://patch.msgid.link/258d931386a512b7089924c70073ca7acba71168.1761045000.git.daniel@makrotopia.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 4cc06901

drivers/net/dsa/lantiq/lantiq_gswip.c

+70 −70
Original line number Diff line number Diff line
@@ -111,12 +111,6 @@ static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 
	MIB_DESC(2, 0x0E, "TxGoodBytes"),

};



static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set,

			      u32 offset)

{

	regmap_write_bits(priv->gswip, offset, clear | set, set);

}



static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset,

				  u32 cleared)

{
@@ -126,18 +120,6 @@ static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 
					!(val & cleared), 20, 50000);

}



static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set,

			    u32 offset)

{

	regmap_write_bits(priv->mdio, offset, clear | set, set);

}



static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,

			   u32 offset)

{

	regmap_write_bits(priv->mii, offset, clear | set, set);

}



static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,

			       int port)

{
@@ -149,7 +131,8 @@ static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 


	reg_port = port + priv->hw_info->mii_port_reg_offset;



	gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(reg_port));

	regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), clear | set,

			  set);

}



static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
@@ -165,13 +148,16 @@ static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 


	switch (reg_port) {

	case 0:

		gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);

		regmap_write_bits(priv->mii, GSWIP_MII_PCDU0, clear | set,

				  set);

		break;

	case 1:

		gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1);

		regmap_write_bits(priv->mii, GSWIP_MII_PCDU1, clear | set,

				  set);

		break;

	case 5:

		gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5);

		regmap_write_bits(priv->mii, GSWIP_MII_PCDU5, clear | set,

				  set);

		break;

	}

}
@@ -287,10 +273,11 @@ static int gswip_pce_table_entry_read(struct gswip_priv *priv, 
		goto out_unlock;



	regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index);

	gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |

				GSWIP_PCE_TBL_CTRL_OPMOD_MASK,

	regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,

			  GSWIP_PCE_TBL_CTRL_ADDR_MASK |

			  GSWIP_PCE_TBL_CTRL_OPMOD_MASK |

			  tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS,

			  GSWIP_PCE_TBL_CTRL);

			  tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS);



	err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL,

				     GSWIP_PCE_TBL_CTRL_BAS);
@@ -348,10 +335,11 @@ static int gswip_pce_table_entry_write(struct gswip_priv *priv, 
	}



	regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index);

	gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |

				GSWIP_PCE_TBL_CTRL_OPMOD_MASK,

	regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,

			  GSWIP_PCE_TBL_CTRL_ADDR_MASK |

			  GSWIP_PCE_TBL_CTRL_OPMOD_MASK |

			  tbl->table | addr_mode,

			  GSWIP_PCE_TBL_CTRL);

			  tbl->table | addr_mode);



	for (i = 0; i < ARRAY_SIZE(tbl->key); i++)

		regmap_write(priv->gswip, GSWIP_PCE_TBL_KEY(i), tbl->key[i]);
@@ -359,10 +347,11 @@ static int gswip_pce_table_entry_write(struct gswip_priv *priv, 
	for (i = 0; i < ARRAY_SIZE(tbl->val); i++)

		regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(i), tbl->val[i]);



	gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |

				GSWIP_PCE_TBL_CTRL_OPMOD_MASK,

	regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,

			  GSWIP_PCE_TBL_CTRL_ADDR_MASK |

			  GSWIP_PCE_TBL_CTRL_OPMOD_MASK |

			  tbl->table | addr_mode,

			  GSWIP_PCE_TBL_CTRL);

			  tbl->table | addr_mode);



	regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, tbl->mask);
@@ -449,8 +438,9 @@ static int gswip_port_enable(struct dsa_switch *ds, int port, 
		if (phydev)

			mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;



		gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,

				GSWIP_MDIO_PHYp(port));

		regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),

				  GSWIP_MDIO_PHY_ADDR_MASK | mdio_phy,

				  mdio_phy);

	}



	/* RMON Counter Enable for port */
@@ -480,9 +470,11 @@ static int gswip_pce_load_microcode(struct gswip_priv *priv) 
	int i;

	int err;



	gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK |

				GSWIP_PCE_TBL_CTRL_OPMOD_MASK,

			  GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);

	regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL,

			  GSWIP_PCE_TBL_CTRL_ADDR_MASK |

			  GSWIP_PCE_TBL_CTRL_OPMOD_MASK |

			  GSWIP_PCE_TBL_CTRL_OPMOD_ADWR,

			  GSWIP_PCE_TBL_CTRL_OPMOD_ADWR);

	regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, 0);



	for (i = 0; i < priv->hw_info->pce_microcode_size; i++) {
@@ -549,9 +541,10 @@ static void gswip_port_commit_pvid(struct gswip_priv *priv, int port) 
	}



	vinr = idx ? GSWIP_PCE_VCTRL_VINR_ALL : GSWIP_PCE_VCTRL_VINR_TAGGED;

	gswip_switch_mask(priv, GSWIP_PCE_VCTRL_VINR,

	regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),

			  GSWIP_PCE_VCTRL_VINR |

			  FIELD_PREP(GSWIP_PCE_VCTRL_VINR, vinr),

			  GSWIP_PCE_VCTRL(port));

			  FIELD_PREP(GSWIP_PCE_VCTRL_VINR, vinr));



	/* Note that in GSWIP 2.2 VLAN mode the VID needs to be programmed

	 * directly instead of referencing the index in the Active VLAN Tablet.
@@ -569,20 +562,27 @@ static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 


	if (vlan_filtering) {

		/* Use tag based VLAN */

		gswip_switch_mask(priv,

				  GSWIP_PCE_VCTRL_VSR,

				  GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |

				  GSWIP_PCE_VCTRL_VEMR | GSWIP_PCE_VCTRL_VID0,

				  GSWIP_PCE_VCTRL(port));

		regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),

				  GSWIP_PCE_VCTRL_VSR |

				  GSWIP_PCE_VCTRL_UVR |

				  GSWIP_PCE_VCTRL_VIMR |

				  GSWIP_PCE_VCTRL_VEMR |

				  GSWIP_PCE_VCTRL_VID0,

				  GSWIP_PCE_VCTRL_UVR |

				  GSWIP_PCE_VCTRL_VIMR |

				  GSWIP_PCE_VCTRL_VEMR |

				  GSWIP_PCE_VCTRL_VID0);

		regmap_clear_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),

				  GSWIP_PCE_PCTRL_0_TVM);

	} else {

		/* Use port based VLAN */

		gswip_switch_mask(priv,

				  GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |

				  GSWIP_PCE_VCTRL_VEMR | GSWIP_PCE_VCTRL_VID0,

		regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port),

				  GSWIP_PCE_VCTRL_UVR |

				  GSWIP_PCE_VCTRL_VIMR |

				  GSWIP_PCE_VCTRL_VEMR |

				  GSWIP_PCE_VCTRL_VID0 |

				  GSWIP_PCE_VCTRL_VSR,

				  GSWIP_PCE_VCTRL(port));

				  GSWIP_PCE_VCTRL_VSR);

		regmap_set_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),

				GSWIP_PCE_PCTRL_0_TVM);

	}
@@ -642,7 +642,7 @@ static int gswip_setup(struct dsa_switch *ds) 
	regmap_write(priv->mdio, GSWIP_MDIO_MDC_CFG0, 0x0);



	/* Configure the MDIO Clock 2.5 MHz */

	gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);

	regmap_write_bits(priv->mdio, GSWIP_MDIO_MDC_CFG1, 0xff | 0x09, 0x09);



	/* bring up the mdio bus */

	err = gswip_mdio(priv);
@@ -1083,8 +1083,9 @@ static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 


	regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port),

			GSWIP_SDMA_PCTRL_EN);

	gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state,

			  GSWIP_PCE_PCTRL_0p(port));

	regmap_write_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port),

			  GSWIP_PCE_PCTRL_0_PSTATE_MASK | stp_state,

			  stp_state);

}



static int gswip_port_fdb(struct dsa_switch *ds, int port,
@@ -1313,8 +1314,8 @@ static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) 
	else

		mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN;



	gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy,

			GSWIP_MDIO_PHYp(port));

	regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),

			  GSWIP_MDIO_PHY_LINK_MASK | mdio_phy, mdio_phy);

}



static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
@@ -1354,11 +1355,11 @@ static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, 
		break;

	}



	gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy,

			GSWIP_MDIO_PHYp(port));

	regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),

			  GSWIP_MDIO_PHY_SPEED_MASK | mdio_phy, mdio_phy);

	gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port);

	gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0,

			  GSWIP_MAC_CTRL_0p(port));

	regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),

			  GSWIP_MAC_CTRL_0_GMII_MASK | mac_ctrl_0, mac_ctrl_0);

}



static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex)
@@ -1373,10 +1374,10 @@ static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) 
		mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS;

	}



	gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0,

			  GSWIP_MAC_CTRL_0p(port));

	gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy,

			GSWIP_MDIO_PHYp(port));

	regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),

			  GSWIP_MAC_CTRL_0_FDUP_MASK | mac_ctrl_0, mac_ctrl_0);

	regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),

			  GSWIP_MDIO_PHY_FDUP_MASK | mdio_phy, mdio_phy);

}



static void gswip_port_set_pause(struct gswip_priv *priv, int port,
@@ -1402,12 +1403,11 @@ static void gswip_port_set_pause(struct gswip_priv *priv, int port, 
			   GSWIP_MDIO_PHY_FCONRX_DIS;

	}



	gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK,

			  mac_ctrl_0, GSWIP_MAC_CTRL_0p(port));

	gswip_mdio_mask(priv,

			GSWIP_MDIO_PHY_FCONTX_MASK |

			GSWIP_MDIO_PHY_FCONRX_MASK,

			mdio_phy, GSWIP_MDIO_PHYp(port));

	regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port),

			  GSWIP_MAC_CTRL_0_FCON_MASK | mac_ctrl_0, mac_ctrl_0);

	regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port),

			  GSWIP_MDIO_PHY_FCONTX_MASK | GSWIP_MDIO_PHY_FCONRX_MASK | mdio_phy,

			  mdio_phy);

}



static void gswip_phylink_mac_config(struct phylink_config *config,
@@ -1526,10 +1526,10 @@ static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 
	int err;



	regmap_write(priv->gswip, GSWIP_BM_RAM_ADDR, index);

	gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK |

				GSWIP_BM_RAM_CTRL_OPMOD,

	regmap_write_bits(priv->gswip, GSWIP_BM_RAM_CTRL,

			  GSWIP_BM_RAM_CTRL_ADDR_MASK | GSWIP_BM_RAM_CTRL_OPMOD |

			  table | GSWIP_BM_RAM_CTRL_BAS,

			      GSWIP_BM_RAM_CTRL);

			  table | GSWIP_BM_RAM_CTRL_BAS);



	err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL,

				     GSWIP_BM_RAM_CTRL_BAS);