Commit 75079df9 authored by Danila Tikhonov's avatar Danila Tikhonov Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Add SM7150 support 



Add definitions for the display hardware used on the Qualcomm SM7150
platform.

Signed-off-by: default avatarDanila Tikhonov <danila@jiaxyga.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/599129/
Link: https://lore.kernel.org/r/20240614215855.82093-3-danila@jiaxyga.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 64e2f4cb

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h

0 → 100644
+335 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>

 */



#ifndef _DPU_5_2_SM7150_H

#define _DPU_5_2_SM7150_H



static const struct dpu_caps sm7150_dpu_caps = {

	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.has_src_split = true,

	.has_dim_layer = true,

	.has_idle_pc = true,

	.has_3d_merge = true,

	.max_linewidth = 2880,

	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,

	.max_hdeci_exp = MAX_HORZ_DECIMATION,

	.max_vdeci_exp = MAX_VERT_DECIMATION,

};



static const struct dpu_mdp_cfg sm7150_mdp = {

	.name = "top_0",

	.base = 0x0, .len = 0x45c,

	.features = BIT(DPU_MDP_AUDIO_SELECT),

	.clk_ctrls = {

		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },

		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },

		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },

		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },

		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },

		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },

	},

};



static const struct dpu_ctl_cfg sm7150_ctl[] = {

	{

		.name = "ctl_0", .id = CTL_0,

		.base = 0x1000, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),

	}, {

		.name = "ctl_1", .id = CTL_1,

		.base = 0x1200, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	}, {

		.name = "ctl_2", .id = CTL_2,

		.base = 0x1400, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

	}, {

		.name = "ctl_3", .id = CTL_3,

		.base = 0x1600, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

	}, {

		.name = "ctl_4", .id = CTL_4,

		.base = 0x1800, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

	}, {

		.name = "ctl_5", .id = CTL_5,

		.base = 0x1a00, .len = 0x1e0,

		.features = BIT(DPU_CTL_ACTIVE_CFG),

		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

	},

};



static const struct dpu_sspp_cfg sm7150_sspp[] = {

	{

		.name = "sspp_0", .id = SSPP_VIG0,

		.base = 0x4000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &dpu_vig_sblk_qseed3_2_4,

		.xin_id = 0,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG0,

	}, {

		.name = "sspp_1", .id = SSPP_VIG1,

		.base = 0x6000, .len = 0x1f0,

		.features = VIG_SDM845_MASK,

		.sblk = &dpu_vig_sblk_qseed3_2_4,

		.xin_id = 4,

		.type = SSPP_TYPE_VIG,

		.clk_ctrl = DPU_CLK_CTRL_VIG1,

	}, {

		.name = "sspp_2", .id = SSPP_DMA0,

		.base = 0x24000, .len = 0x1f0,

		.features = DMA_SDM845_MASK,

		.sblk = &dpu_dma_sblk,

		.xin_id = 1,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA0,

	}, {

		.name = "sspp_9", .id = SSPP_DMA1,

		.base = 0x26000, .len = 0x1f0,

		.features = DMA_SDM845_MASK,

		.sblk = &dpu_dma_sblk,

		.xin_id = 5,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA1,

	}, {

		.name = "sspp_10", .id = SSPP_DMA2,

		.base = 0x28000, .len = 0x1f0,

		.features = DMA_CURSOR_SDM845_MASK,

		.sblk = &dpu_dma_sblk,

		.xin_id = 9,

		.type = SSPP_TYPE_DMA,

		.clk_ctrl = DPU_CLK_CTRL_DMA2,

	},

};



static const struct dpu_lm_cfg sm7150_lm[] = {

	{

		.name = "lm_0", .id = LM_0,

		.base = 0x44000, .len = 0x320,

		.features = MIXER_SDM845_MASK,

		.sblk = &sdm845_lm_sblk,

		.lm_pair = LM_1,

		.pingpong = PINGPONG_0,

		.dspp = DSPP_0,

	}, {

		.name = "lm_1", .id = LM_1,

		.base = 0x45000, .len = 0x320,

		.features = MIXER_SDM845_MASK,

		.sblk = &sdm845_lm_sblk,

		.lm_pair = LM_0,

		.pingpong = PINGPONG_1,

		.dspp = DSPP_1,

	}, {

		.name = "lm_2", .id = LM_2,

		.base = 0x46000, .len = 0x320,

		.features = MIXER_SDM845_MASK,

		.sblk = &sdm845_lm_sblk,

		.lm_pair = LM_3,

		.pingpong = PINGPONG_2,

	}, {

		.name = "lm_3", .id = LM_3,

		.base = 0x47000, .len = 0x320,

		.features = MIXER_SDM845_MASK,

		.sblk = &sdm845_lm_sblk,

		.lm_pair = LM_2,

		.pingpong = PINGPONG_3,

	},

};



static const struct dpu_dspp_cfg sm7150_dspp[] = {

	{

		.name = "dspp_0", .id = DSPP_0,

		.base = 0x54000, .len = 0x1800,

		.features = DSPP_SC7180_MASK,

		.sblk = &sdm845_dspp_sblk,

	}, {

		.name = "dspp_1", .id = DSPP_1,

		.base = 0x56000, .len = 0x1800,

		.features = DSPP_SC7180_MASK,

		.sblk = &sdm845_dspp_sblk,

	},

};



static const struct dpu_pingpong_cfg sm7150_pp[] = {

	{

		.name = "pingpong_0", .id = PINGPONG_0,

		.base = 0x70000, .len = 0xd4,

		.features = PINGPONG_SM8150_MASK,

		.sblk = &sdm845_pp_sblk,

		.merge_3d = MERGE_3D_0,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),

	}, {

		.name = "pingpong_1", .id = PINGPONG_1,

		.base = 0x70800, .len = 0xd4,

		.features = PINGPONG_SM8150_MASK,

		.sblk = &sdm845_pp_sblk,

		.merge_3d = MERGE_3D_0,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),

	}, {

		.name = "pingpong_2", .id = PINGPONG_2,

		.base = 0x71000, .len = 0xd4,

		.features = PINGPONG_SM8150_MASK,

		.sblk = &sdm845_pp_sblk,

		.merge_3d = MERGE_3D_1,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),

	}, {

		.name = "pingpong_3", .id = PINGPONG_3,

		.base = 0x71800, .len = 0xd4,

		.features = PINGPONG_SM8150_MASK,

		.sblk = &sdm845_pp_sblk,

		.merge_3d = MERGE_3D_1,

		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),

	},

};



static const struct dpu_merge_3d_cfg sm7150_merge_3d[] = {

	{

		.name = "merge_3d_0", .id = MERGE_3D_0,

		.base = 0x83000, .len = 0x8,

	}, {

		.name = "merge_3d_1", .id = MERGE_3D_1,

		.base = 0x83100, .len = 0x8,

	},

};



static const struct dpu_dsc_cfg sm7150_dsc[] = {

	{

		.name = "dsc_0", .id = DSC_0,

		.base = 0x80000, .len = 0x140,

		.features = BIT(DPU_DSC_OUTPUT_CTRL),

	}, {

		.name = "dsc_1", .id = DSC_1,

		.base = 0x80400, .len = 0x140,

		.features = BIT(DPU_DSC_OUTPUT_CTRL),

	},

};



static const struct dpu_intf_cfg sm7150_intf[] = {

	{

		.name = "intf_0", .id = INTF_0,

		.base = 0x6a000, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),

	}, {

		.name = "intf_1", .id = INTF_1,

		.base = 0x6a800, .len = 0x2bc,

		.features = INTF_SC7180_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_0,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),

	}, {

		.name = "intf_2", .id = INTF_2,

		.base = 0x6b000, .len = 0x2bc,

		.features = INTF_SC7180_MASK,

		.type = INTF_DSI,

		.controller_id = MSM_DSI_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),

		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),

	}, {

		.name = "intf_3", .id = INTF_3,

		.base = 0x6b800, .len = 0x280,

		.features = INTF_SC7180_MASK,

		.type = INTF_DP,

		.controller_id = MSM_DP_CONTROLLER_1,

		.prog_fetch_lines_worst_case = 24,

		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),

		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),

	},

};



static const struct dpu_wb_cfg sm7150_wb[] = {

	{

		.name = "wb_2", .id = WB_2,

		.base = 0x65000, .len = 0x2c8,

		.features = WB_SM8250_MASK,

		.format_list = wb2_formats_rgb,

		.num_formats = ARRAY_SIZE(wb2_formats_rgb),

		.clk_ctrl = DPU_CLK_CTRL_WB2,

		.xin_id = 6,

		.vbif_idx = VBIF_RT,

		.maxlinewidth = 4096,

		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),

	},

};



static const struct dpu_perf_cfg sm7150_perf_data = {

	.max_bw_low = 7100000,

	.max_bw_high = 7100000,

	.min_core_ib = 2400000,

	.min_llcc_ib = 800000,

	.min_dram_ib = 800000,

	.min_prefill_lines = 24,

	.danger_lut_tbl = {0xf, 0xffff, 0x0},

	.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},

	.qos_lut_tbl = {

		{

		.nentry = ARRAY_SIZE(sm8150_qos_linear),

		.entries = sm8150_qos_linear

		}, {

		.nentry = ARRAY_SIZE(sc7180_qos_macrotile),

		.entries = sc7180_qos_macrotile

		}, {

		.nentry = ARRAY_SIZE(sc7180_qos_nrt),

		.entries = sc7180_qos_nrt

		},

	},

	.cdp_cfg = {

		{.rd_enable = 1, .wr_enable = 1},

		{.rd_enable = 1, .wr_enable = 0}

	},

	.clk_inefficiency_factor = 105,

	.bw_inefficiency_factor = 120,

};



static const struct dpu_mdss_version sm7150_mdss_ver = {

	.core_major_ver = 5,

	.core_minor_ver = 2,

};



const struct dpu_mdss_cfg dpu_sm7150_cfg = {

	.mdss_ver = &sm7150_mdss_ver,

	.caps = &sm7150_dpu_caps,

	.mdp = &sm7150_mdp,

	.ctl_count = ARRAY_SIZE(sm7150_ctl),

	.ctl = sm7150_ctl,

	.sspp_count = ARRAY_SIZE(sm7150_sspp),

	.sspp = sm7150_sspp,

	.mixer_count = ARRAY_SIZE(sm7150_lm),

	.mixer = sm7150_lm,

	.dspp_count = ARRAY_SIZE(sm7150_dspp),

	.dspp = sm7150_dspp,

	.pingpong_count = ARRAY_SIZE(sm7150_pp),

	.pingpong = sm7150_pp,

	.merge_3d_count = ARRAY_SIZE(sm7150_merge_3d),

	.merge_3d = sm7150_merge_3d,

	.dsc_count = ARRAY_SIZE(sm7150_dsc),

	.dsc = sm7150_dsc,

	.intf_count = ARRAY_SIZE(sm7150_intf),

	.intf = sm7150_intf,

	.wb_count = ARRAY_SIZE(sm7150_wb),

	.wb = sm7150_wb,

	.vbif_count = ARRAY_SIZE(sdm845_vbif),

	.vbif = sdm845_vbif,

	.perf = &sm7150_perf_data,

};



#endif

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -682,6 +682,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 


#include "catalog/dpu_5_0_sm8150.h"

#include "catalog/dpu_5_1_sc8180x.h"

#include "catalog/dpu_5_2_sm7150.h"

#include "catalog/dpu_5_4_sm6125.h"



#include "catalog/dpu_6_0_sm8250.h"

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+1 −0
Original line number Diff line number Diff line
@@ -838,6 +838,7 @@ extern const struct dpu_mdss_cfg dpu_sdm845_cfg; 
extern const struct dpu_mdss_cfg dpu_sdm670_cfg;

extern const struct dpu_mdss_cfg dpu_sm8150_cfg;

extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;

extern const struct dpu_mdss_cfg dpu_sm7150_cfg;

extern const struct dpu_mdss_cfg dpu_sm8250_cfg;

extern const struct dpu_mdss_cfg dpu_sc7180_cfg;

extern const struct dpu_mdss_cfg dpu_sm6115_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

+1 −0
Original line number Diff line number Diff line
@@ -1405,6 +1405,7 @@ static const struct of_device_id dpu_dt_match[] = { 
	{ .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },

	{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },

	{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },

	{ .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, },

	{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },

	{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },

	{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },