Commit 7517e899 authored by Xiaochen Shen's avatar Xiaochen Shen Committed by Borislav Petkov (AMD)
Browse files

x86/resctrl: Fix memory bandwidth counter width for Hygon 



The memory bandwidth calculation relies on reading the hardware counter
and measuring the delta between samples. To ensure accurate measurement,
the software reads the counter frequently enough to prevent it from
rolling over twice between reads.

The default Memory Bandwidth Monitoring (MBM) counter width is 24 bits.
Hygon CPUs provide a 32-bit width counter, but they do not support the
MBM capability CPUID leaf (0xF.[ECX=1]:EAX) to report the width offset
(from 24 bits).

Consequently, the kernel falls back to the 24-bit default counter width,
which causes incorrect overflow handling on Hygon CPUs.

Fix this by explicitly setting the counter width offset to 8 bits (resulting
in a 32-bit total counter width) for Hygon CPUs.

Fixes: d8df1263 ("x86/cpu/hygon: Add missing resctrl_cpu_detect() in bsp_init helper")
Signed-off-by: default avatarXiaochen Shen <shenxiaochen@open-hieco.net>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarTony Luck <tony.luck@intel.com>
Reviewed-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251209062650.1536952-3-shenxiaochen@open-hieco.net
parent 6ee98aab

arch/x86/kernel/cpu/resctrl/core.c

+13 −2
Original line number Diff line number Diff line
@@ -1021,8 +1021,19 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c) 
		c->x86_cache_occ_scale = ebx;

		c->x86_cache_mbm_width_offset = eax & 0xff;



		if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset)

		if (!c->x86_cache_mbm_width_offset) {

			switch (c->x86_vendor) {

			case X86_VENDOR_AMD:

				c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;

				break;

			case X86_VENDOR_HYGON:

				c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_HYGON;

				break;

			default:

				/* Leave c->x86_cache_mbm_width_offset as 0 */

				break;

			}

		}

	}

}

arch/x86/kernel/cpu/resctrl/internal.h

+3 −0
Original line number Diff line number Diff line
@@ -14,6 +14,9 @@ 


#define MBM_CNTR_WIDTH_OFFSET_AMD	20



/* Hygon MBM counter width as an offset from MBM_CNTR_WIDTH_BASE */

#define MBM_CNTR_WIDTH_OFFSET_HYGON	8



#define RMID_VAL_ERROR			BIT_ULL(63)



#define RMID_VAL_UNAVAIL		BIT_ULL(62)