Commit 7520803b authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Add handling of LM_6 and LM_7 bits in pending flush mask 



MDSS/MDP v12 comes with new bits in flush registers (e.g.
MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarJessica Zhang <quic_jesszhan@quicinc.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/651260/
Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-13-8cab30c3e4df@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent a5539d0f

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

+6 −0
Original line number Diff line number Diff line
@@ -261,6 +261,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(struct dpu_hw_ctl *ctx, 
	case LM_5:

		ctx->pending_flush_mask |= BIT(20);

		break;

	case LM_6:

		ctx->pending_flush_mask |= BIT(21);

		break;

	case LM_7:

		ctx->pending_flush_mask |= BIT(27);

		break;

	default:

		break;

	}