Commit 754c366e authored by Sonny Jiang's avatar Sonny Jiang Committed by Alex Deucher
Browse files

drm/amdgpu: update fw_share for VCN5 



kmd_fw_shared changed in VCN5

Signed-off-by: default avatarSonny Jiang <sonny.jiang@amd.com>
Reviewed-by: default avatarRuijing Dong <ruijing.dong@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 770e6c44

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+4 −1
Original line number Diff line number Diff line
@@ -185,7 +185,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)

		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);



	if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) {

	if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(5, 0, 0)) {

		fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared));

		log_offset = offsetof(struct amdgpu_vcn5_fw_shared, fw_log);

	} else if (amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0)) {

		fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));

		log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);

	} else {

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+10 −0
Original line number Diff line number Diff line
@@ -454,6 +454,16 @@ struct amdgpu_vcn_rb_metadata { 
	uint8_t pad[26];

};



struct amdgpu_vcn5_fw_shared {

	uint32_t present_flag_0;

	uint8_t pad[12];

	struct amdgpu_fw_shared_unified_queue_struct sq;

	uint8_t pad1[8];

	struct amdgpu_fw_shared_fw_logging fw_log;

	struct amdgpu_fw_shared_rb_setup rb_setup;

	uint8_t pad2[4];

};



#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80

#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40

#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

+7 −7
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ static int vcn_v5_0_0_sw_init(void *handle) 
		return r;



	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

		volatile struct amdgpu_vcn4_fw_shared *fw_shared;

		volatile struct amdgpu_vcn5_fw_shared *fw_shared;



		if (adev->vcn.harvest_config & (1 << i))

			continue;
@@ -154,7 +154,7 @@ static int vcn_v5_0_0_sw_fini(void *handle) 


	if (drm_dev_enter(adev_to_drm(adev), &idx)) {

		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {

			volatile struct amdgpu_vcn4_fw_shared *fw_shared;

			volatile struct amdgpu_vcn5_fw_shared *fw_shared;



			if (adev->vcn.harvest_config & (1 << i))

				continue;
@@ -335,7 +335,7 @@ static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst) 
		upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));

	WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);

	WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,

		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));

		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)));

}



/**
@@ -439,7 +439,7 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i 
		VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);

	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(

		VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),

		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);

		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect);



	/* VCN global tiling registers */

	WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(
@@ -616,7 +616,7 @@ static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 
 */

static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)

{

	volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

	volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;

	struct amdgpu_ring *ring;

	uint32_t tmp;
@@ -713,7 +713,7 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b 
 */

static int vcn_v5_0_0_start(struct amdgpu_device *adev)

{

	volatile struct amdgpu_vcn4_fw_shared *fw_shared;

	volatile struct amdgpu_vcn5_fw_shared *fw_shared;

	struct amdgpu_ring *ring;

	uint32_t tmp;

	int i, j, k, r;
@@ -894,7 +894,7 @@ static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 
 */

static int vcn_v5_0_0_stop(struct amdgpu_device *adev)

{

	volatile struct amdgpu_vcn4_fw_shared *fw_shared;

	volatile struct amdgpu_vcn5_fw_shared *fw_shared;

	uint32_t tmp;

	int i, r = 0;