Commit 7554d532 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Bjorn Andersson
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clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks 



Add the Q6 BIMC, LPASS core/adsp SMMU clocks to support audio related
functionality on MSM8998 and APQ variants.

As a final step to entirely enable the required clock tree for the
lpass iommu and audio dsp, add the lpass core/adsp GDSCs.

As a side note, it was found out that disabling the lpass core GDSC
at any time would cause a system lockup (and reboot): disabling
this GDSC will leave the lpass iommu completely unclocked, losing
its state entirely - including the secure contexts that have been
previously set-up from the bootloader/TrustZone.
Losing this IOMMU configuration will trigger a hypervisor fault,
which will reboot the system; the only workaround for this issue
is to declare the lpass core gdsc as always-on.

It should also not be forgotten that this is all about firmware and
there may be a version of it that doesn't enable this GDSC at all
before booting Linux, which is the reason why this specific declaration
wasn't simply omitted.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: default avatarMarc Gonzalez <mgonzalez@freebox.fr>
Link: https://lore.kernel.org/r/20240814-lpass-v1-2-a5bb8f9dfa8b@freebox.fr


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 2cb4fcc4

drivers/clk/qcom/gcc-msm8998.c

+62 −0
Original line number Diff line number Diff line
@@ -2922,6 +2922,43 @@ static struct clk_branch ssc_cnoc_ahbs_clk = { 
	},

};



static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {

	.halt_reg = 0x7D010,

	.clkr = {

		.enable_reg = 0x7D010,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data) {

			.name = "hlos1_vote_lpass_core_smmu_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {

	.halt_reg = 0x7D014,

	.clkr = {

		.enable_reg = 0x7D014,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data) {

			.name = "hlos1_vote_lpass_adsp_smmu_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_mss_q6_bimc_axi_clk = {

	.halt_reg = 0x8A040,

	.clkr = {

		.enable_reg = 0x8A040,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data) {

			.name = "gcc_mss_q6_bimc_axi_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct gdsc pcie_0_gdsc = {

	.gdscr = 0x6b004,

	.gds_hw_ctrl = 0x0,
@@ -2953,6 +2990,26 @@ static struct gdsc usb_30_gdsc = { 
	.flags = VOTABLE,

};



static struct gdsc hlos1_vote_lpass_adsp = {

	.gdscr = 0x7d034,

	.gds_hw_ctrl = 0x0,

	.pd = {

		.name = "lpass_adsp_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = VOTABLE,

};



static struct gdsc hlos1_vote_lpass_core = {

	.gdscr = 0x7d038,

	.gds_hw_ctrl = 0x0,

	.pd = {

		.name = "lpass_core_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.flags = ALWAYS_ON,

};



static struct clk_regmap *gcc_msm8998_clocks[] = {

	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,

	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
@@ -3133,12 +3190,17 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { 
	[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,

	[GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,

	[GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,

	[HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &hlos1_vote_lpass_core_smmu_clk.clkr,

	[HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr,

	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,

};



static struct gdsc *gcc_msm8998_gdscs[] = {

	[PCIE_0_GDSC] = &pcie_0_gdsc,

	[UFS_GDSC] = &ufs_gdsc,

	[USB_30_GDSC] = &usb_30_gdsc,

	[LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp,

	[LPASS_CORE_GDSC] = &hlos1_vote_lpass_core,

};



static const struct qcom_reset_map gcc_msm8998_resets[] = {