Unverified Commit 756485bf authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Krzysztof Wilczyński
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dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema 

Move SC7280 PCIe devices from qcom,pcie.yaml binding to a dedicated file
to make reviewing easier.

This creates equivalent schema file, except:
 - Missing required compatible which is actually redundant.
 - Expecting exactly one MSI interrupt, instead of eight, because I
   could not find interrupt details for this model and current DTS uses
   one interrupt.

Link: https://lore.kernel.org/linux-pci/20240205-dt-bindings-pci-qcom-split-continued-v1-2-c333cab5eeea@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
parent d5e74915

Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml

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+166 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SC7280 PCI Express Root Complex



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description:

  Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys

  DesignWare PCIe IP.



properties:

  compatible:

    const: qcom,pcie-sc7280



  reg:

    minItems: 5

    maxItems: 6



  reg-names:

    minItems: 5

    items:

      - const: parf # Qualcomm specific registers

      - const: dbi # DesignWare PCIe registers

      - const: elbi # External local bus interface registers

      - const: atu # ATU address space

      - const: config # PCIe configuration space

      - const: mhi # MHI registers



  clocks:

    minItems: 13

    maxItems: 13



  clock-names:

    items:

      - const: pipe # PIPE clock

      - const: pipe_mux # PIPE MUX

      - const: phy_pipe # PIPE output clock

      - const: ref # REFERENCE clock

      - const: aux # Auxiliary clock

      - const: cfg # Configuration clock

      - const: bus_master # Master AXI clock

      - const: bus_slave # Slave AXI clock

      - const: slave_q2a # Slave Q2A clock

      - const: tbu # PCIe TBU clock

      - const: ddrss_sf_tbu # PCIe SF TBU clock

      - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock

      - const: aggre1 # Aggre NoC PCIe1 AXI clock



  interrupts:

    maxItems: 1



  interrupt-names:

    items:

      - const: msi



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: pci



  vddpe-3v3-supply:

    description: PCIe endpoint power supply



allOf:

  - $ref: qcom,pcie-common.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sc7280.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie@1c08000 {

            compatible = "qcom,pcie-sc7280";

            reg = <0 0x01c08000 0 0x3000>,

                  <0 0x40000000 0 0xf1d>,

                  <0 0x40000f20 0 0xa8>,

                  <0 0x40001000 0 0x1000>,

                  <0 0x40100000 0 0x100000>;

            reg-names = "parf", "dbi", "elbi", "atu", "config";

            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,

                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;



            bus-range = <0x00 0xff>;

            device_type = "pci";

            linux,pci-domain = <1>;

            num-lanes = <2>;



            #address-cells = <3>;

            #size-cells = <2>;



            assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;

            assigned-clock-rates = <19200000>;



            clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,

                     <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,

                     <&pcie1_phy>,

                     <&rpmhcc RPMH_CXO_CLK>,

                     <&gcc GCC_PCIE_1_AUX_CLK>,

                     <&gcc GCC_PCIE_1_CFG_AHB_CLK>,

                     <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,

                     <&gcc GCC_PCIE_1_SLV_AXI_CLK>,

                     <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,

                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

                     <&gcc GCC_DDRSS_PCIE_SF_CLK>,

                     <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,

                     <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;



            clock-names = "pipe",

                          "pipe_mux",

                          "phy_pipe",

                          "ref",

                          "aux",

                          "cfg",

                          "bus_master",

                          "bus_slave",

                          "slave_q2a",

                          "tbu",

                          "ddrss_sf_tbu",

                          "aggre0",

                          "aggre1";



            dma-coherent;



            interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "msi";

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 0x7>;

            interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;



            iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,

                        <0x100 &apps_smmu 0x1c81 0x1>;



            phys = <&pcie1_phy>;

            phy-names = "pciephy";



            pinctrl-names = "default";

            pinctrl-0 = <&pcie1_clkreq_n>;



            power-domains = <&gcc GCC_PCIE_1_GDSC>;



            resets = <&gcc GCC_PCIE_1_BCR>;

            reset-names = "pci";



            perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;

            vddpe-3v3-supply = <&pp3300_ssd>;

        };

    };

Documentation/devicetree/bindings/pci/qcom,pcie.yaml

+0 −38
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ properties: 
          - qcom,pcie-msm8996

          - qcom,pcie-qcs404

          - qcom,pcie-sa8775p

          - qcom,pcie-sc7280

          - qcom,pcie-sdm845

          - qcom,pcie-sdx55

      - items:
@@ -93,9 +92,6 @@ properties: 
  vdda_refclk-supply:

    description: A phandle to the core analog power supply for IC which generates reference clock



  vddpe-3v3-supply:

    description: A phandle to the PCIe endpoint power supply



  phys:

    maxItems: 1
@@ -205,7 +201,6 @@ allOf: 
          contains:

            enum:

              - qcom,pcie-sa8775p

              - qcom,pcie-sc7280

              - qcom,pcie-sdx55

    then:

      properties:
@@ -431,38 +426,6 @@ allOf: 
            - const: pwr # PWR reset

            - const: ahb # AHB reset



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,pcie-sc7280

    then:

      properties:

        clocks:

          minItems: 13

          maxItems: 13

        clock-names:

          items:

            - const: pipe # PIPE clock

            - const: pipe_mux # PIPE MUX

            - const: phy_pipe # PIPE output clock

            - const: ref # REFERENCE clock

            - const: aux # Auxiliary clock

            - const: cfg # Configuration clock

            - const: bus_master # Master AXI clock

            - const: bus_slave # Slave AXI clock

            - const: slave_q2a # Slave Q2A clock

            - const: tbu # PCIe TBU clock

            - const: ddrss_sf_tbu # PCIe SF TBU clock

            - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock

            - const: aggre1 # Aggre NoC PCIe1 AXI clock

        resets:

          maxItems: 1

        reset-names:

          items:

            - const: pci # PCIe core reset



  - if:

      properties:

        compatible:
@@ -603,7 +566,6 @@ allOf: 
            enum:

              - qcom,pcie-msm8996

              - qcom,pcie-sa8775p

              - qcom,pcie-sc7280

              - qcom,pcie-sdm845

    then:

      oneOf: