Commit 757af27b authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Fix rest of pass-by-value structs in DML 



Passing structs adds a lot of overhead. We don't ever want to pass
anything bigger than primitives by value.

This patch fixes these Coverity IDs:
Addresses-Coverity-ID: 1424031: ("Big parameter passed by value")
Addresses-Coverity-ID: 1424055: ("Big parameter passed by value")
Addresses-Coverity-ID: 1424072: ("Big parameter passed by value")
Addresses-Coverity-ID: 1423779: ("Big parameter passed by value")

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Cc: Nick Desaulniers <ndesaulniers@google.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: amd-gfx@lists.freedesktop.org
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Cc: Arnd Bergmann <arnd@kernel.org>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Xinhui Pan <Xinhui.Pan@amd.com>
Cc: Nathan Chancellor <nathan@kernel.org>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: llvm@lists.linux.dev
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Build-tested-by: default avatarNathan Chancellor <nathan@kernel.org>
Reviewed-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4768349e

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+5 −5
Original line number Diff line number Diff line
@@ -502,15 +502,15 @@ static void dcn_bw_calc_rq_dlg_ttu( 
	/*todo: soc->sr_enter_plus_exit_time??*/

	dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;



	dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);

	dml1_extract_rq_regs(dml, rq_regs, rq_param);

	dml1_rq_dlg_get_rq_params(dml, &rq_param, &input.pipe.src);

	dml1_extract_rq_regs(dml, rq_regs, &rq_param);

	dml1_rq_dlg_get_dlg_params(

			dml,

			dlg_regs,

			ttu_regs,

			rq_param.dlg,

			dlg_sys_param,

			input,

			&rq_param.dlg,

			&dlg_sys_param,

			&input,

			true,

			true,

			v->pte_enable == dcn_bw_yes,

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

+63 −63
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ 
static void dml20_rq_dlg_get_rq_params(

		struct display_mode_lib *mode_lib,

		display_rq_params_st *rq_param,

		const display_pipe_source_params_st pipe_src_param);

		const display_pipe_source_params_st *pipe_src_param);



// Function: dml20_rq_dlg_get_dlg_params

//  Calculate deadline related parameters
@@ -49,8 +49,8 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
		const unsigned int pipe_idx,

		display_dlg_regs_st *disp_dlg_regs,

		display_ttu_regs_st *disp_ttu_regs,

		const display_rq_dlg_params_st rq_dlg_param,

		const display_dlg_sys_params_st dlg_sys_param,

		const display_rq_dlg_params_st *rq_dlg_param,

		const display_dlg_sys_params_st *dlg_sys_param,

		const bool cstate_en,

		const bool pstate_en);

/*
@@ -188,28 +188,28 @@ static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, 


static void extract_rq_regs(struct display_mode_lib *mode_lib,

		display_rq_regs_st *rq_regs,

		const display_rq_params_st rq_param)

		const display_rq_params_st *rq_param)

{

	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;

	unsigned int detile_buf_plane1_addr = 0;



	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l);

	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l);



	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),

	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height),

			1) - 3;



	if (rq_param.yuv420) {

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c);

		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),

	if (rq_param->yuv420) {

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c);

		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height),

				1) - 3;

	}



	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);

	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);

	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height);

	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height);



	// TODO: take the max between luma, chroma chunk size?

	// okay for now, as we are setting chunk_bytes to 8kb anyways

	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb

	if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb

		rq_regs->drq_expansion_mode = 0;

	} else {

		rq_regs->drq_expansion_mode = 2;
@@ -218,9 +218,9 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, 
	rq_regs->mrq_expansion_mode = 1;

	rq_regs->crq_expansion_mode = 1;



	if (rq_param.yuv420) {

		if ((double) rq_param.misc.rq_l.stored_swath_bytes

				/ (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {

	if (rq_param->yuv420) {

		if ((double) rq_param->misc.rq_l.stored_swath_bytes

				/ (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) {

			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma

		} else {

			detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
@@ -233,7 +233,7 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, 


static void handle_det_buf_split(struct display_mode_lib *mode_lib,

		display_rq_params_st *rq_param,

		const display_pipe_source_params_st pipe_src_param)

		const display_pipe_source_params_st *pipe_src_param)

{

	unsigned int total_swath_bytes = 0;

	unsigned int swath_bytes_l = 0;
@@ -242,8 +242,8 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, 
	unsigned int full_swath_bytes_packed_c = 0;

	bool req128_l = false;

	bool req128_c = false;

	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);

	bool surf_vert = (pipe_src_param.source_scan == dm_vert);

	bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

	bool surf_vert = (pipe_src_param->source_scan == dm_vert);

	unsigned int log2_swath_height_l = 0;

	unsigned int log2_swath_height_c = 0;

	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
@@ -685,7 +685,7 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, 
		display_data_rq_sizing_params_st *rq_sizing_param,

		display_data_rq_dlg_params_st *rq_dlg_param,

		display_data_rq_misc_params_st *rq_misc_param,

		const display_pipe_source_params_st pipe_src_param,

		const display_pipe_source_params_st *pipe_src_param,

		bool is_chroma)

{

	bool mode_422 = false;
@@ -697,15 +697,15 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, 


	// TODO check if ppe apply for both luma and chroma in 422 case

	if (is_chroma) {

		vp_width = pipe_src_param.viewport_width_c / ppe;

		vp_height = pipe_src_param.viewport_height_c;

		data_pitch = pipe_src_param.data_pitch_c;

		meta_pitch = pipe_src_param.meta_pitch_c;

		vp_width = pipe_src_param->viewport_width_c / ppe;

		vp_height = pipe_src_param->viewport_height_c;

		data_pitch = pipe_src_param->data_pitch_c;

		meta_pitch = pipe_src_param->meta_pitch_c;

	} else {

		vp_width = pipe_src_param.viewport_width / ppe;

		vp_height = pipe_src_param.viewport_height;

		data_pitch = pipe_src_param.data_pitch;

		meta_pitch = pipe_src_param.meta_pitch;

		vp_width = pipe_src_param->viewport_width / ppe;

		vp_height = pipe_src_param->viewport_height;

		data_pitch = pipe_src_param->data_pitch;

		meta_pitch = pipe_src_param->meta_pitch;

	}



	rq_sizing_param->chunk_bytes = 8192;
@@ -728,21 +728,21 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, 
			vp_height,

			data_pitch,

			meta_pitch,

			pipe_src_param.source_format,

			pipe_src_param.sw_mode,

			pipe_src_param.macro_tile_size,

			pipe_src_param.source_scan,

			pipe_src_param->source_format,

			pipe_src_param->sw_mode,

			pipe_src_param->macro_tile_size,

			pipe_src_param->source_scan,

			is_chroma);

}



static void dml20_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,

		display_rq_params_st *rq_param,

		const display_pipe_source_params_st pipe_src_param)

		const display_pipe_source_params_st *pipe_src_param)

{

	// get param for luma surface

	rq_param->yuv420 = pipe_src_param.source_format == dm_420_8

			|| pipe_src_param.source_format == dm_420_10;

	rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;

	rq_param->yuv420 = pipe_src_param->source_format == dm_420_8

			|| pipe_src_param->source_format == dm_420_10;

	rq_param->yuv420_10bpc = pipe_src_param->source_format == dm_420_10;



	get_surf_rq_param(mode_lib,

			&(rq_param->sizing.rq_l),
@@ -751,7 +751,7 @@ static void dml20_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 
			pipe_src_param,

			0);



	if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {

	if (is_dual_plane((enum source_format_class)(pipe_src_param->source_format))) {

		// get param for chroma surface

		get_surf_rq_param(mode_lib,

				&(rq_param->sizing.rq_c),
@@ -773,8 +773,8 @@ void dml20_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 
	display_rq_params_st rq_param = {0};



	memset(rq_regs, 0, sizeof(*rq_regs));

	dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param->src);

	extract_rq_regs(mode_lib, rq_regs, rq_param);

	dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, &pipe_param->src);

	extract_rq_regs(mode_lib, rq_regs, &rq_param);



	print__rq_regs_st(mode_lib, rq_regs);

}
@@ -787,8 +787,8 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
		const unsigned int pipe_idx,

		display_dlg_regs_st *disp_dlg_regs,

		display_ttu_regs_st *disp_ttu_regs,

		const display_rq_dlg_params_st rq_dlg_param,

		const display_dlg_sys_params_st dlg_sys_param,

		const display_rq_dlg_params_st *rq_dlg_param,

		const display_dlg_sys_params_st *dlg_sys_param,

		const bool cstate_en,

		const bool pstate_en)

{
@@ -935,7 +935,7 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
			* (double) ref_freq_to_pix_freq);

	ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));



	min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;

	min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz;

	t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);

	min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
@@ -995,20 +995,20 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
//     vinit_bot_l     = scl.vinit_bot;

//     vinit_bot_c     = scl.vinit_bot_c;



//    unsigned int swath_height_l                 = rq_dlg_param.rq_l.swath_height;

	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;

//    unsigned int dpte_bytes_per_row_ub_l        = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;

	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;

//    unsigned int meta_pte_bytes_per_frame_ub_l  = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;

//    unsigned int meta_bytes_per_row_ub_l        = rq_dlg_param.rq_l.meta_bytes_per_row_ub;

//    unsigned int swath_height_l                 = rq_dlg_param->rq_l.swath_height;

	swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub;

//    unsigned int dpte_bytes_per_row_ub_l        = rq_dlg_param->rq_l.dpte_bytes_per_row_ub;

	dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub;

//    unsigned int meta_pte_bytes_per_frame_ub_l  = rq_dlg_param->rq_l.meta_pte_bytes_per_frame_ub;

//    unsigned int meta_bytes_per_row_ub_l        = rq_dlg_param->rq_l.meta_bytes_per_row_ub;



//    unsigned int swath_height_c                 = rq_dlg_param.rq_c.swath_height;

	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;

	//   dpte_bytes_per_row_ub_c        = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;

	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;

//    unsigned int swath_height_c                 = rq_dlg_param->rq_c.swath_height;

	swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub;

	//   dpte_bytes_per_row_ub_c        = rq_dlg_param->rq_c.dpte_bytes_per_row_ub;

	dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub;



	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;

	meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;

	meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub;

	meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub;

	vupdate_offset = dst->vupdate_offset;

	vupdate_width = dst->vupdate_width;

	vready_offset = dst->vready_offset;
@@ -1137,16 +1137,16 @@ static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
	dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);



	// Active

	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;

	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;

	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;

	meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;

	req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub;

	req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub;

	meta_row_height_l = rq_dlg_param->rq_l.meta_row_height;

	meta_row_height_c = rq_dlg_param->rq_c.meta_row_height;

	swath_width_pixels_ub_l = 0;

	swath_width_pixels_ub_c = 0;

	scaler_rec_in_width_l = 0;

	scaler_rec_in_width_c = 0;

	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;

	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;

	dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height;

	dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height;



	if (mode_422) {

		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
@@ -1584,15 +1584,15 @@ void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 
	// system parameter calculation done



	dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);

	dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src);

	dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe.src);

	dml20_rq_dlg_get_dlg_params(mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx,

			dlg_regs,

			ttu_regs,

			rq_param.dlg,

			dlg_sys_param,

			&rq_param.dlg,

			&dlg_sys_param,

			cstate_en,

			pstate_en);

	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

+62 −62
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ 
static void dml20v2_rq_dlg_get_rq_params(

		struct display_mode_lib *mode_lib,

		display_rq_params_st * rq_param,

		const display_pipe_source_params_st pipe_src_param);

		const display_pipe_source_params_st *pipe_src_param);



// Function: dml20v2_rq_dlg_get_dlg_params

//  Calculate deadline related parameters
@@ -49,8 +49,8 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
		const unsigned int pipe_idx,

		display_dlg_regs_st *disp_dlg_regs,

		display_ttu_regs_st *disp_ttu_regs,

		const display_rq_dlg_params_st rq_dlg_param,

		const display_dlg_sys_params_st dlg_sys_param,

		const display_rq_dlg_params_st *rq_dlg_param,

		const display_dlg_sys_params_st *dlg_sys_param,

		const bool cstate_en,

		const bool pstate_en);

/*
@@ -188,28 +188,28 @@ static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, 


static void extract_rq_regs(struct display_mode_lib *mode_lib,

		display_rq_regs_st *rq_regs,

		const display_rq_params_st rq_param)

		const display_rq_params_st *rq_param)

{

	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;

	unsigned int detile_buf_plane1_addr = 0;



	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param.sizing.rq_l);

	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l);



	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),

	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height),

			1) - 3;



	if (rq_param.yuv420) {

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param.sizing.rq_c);

		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),

	if (rq_param->yuv420) {

		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c);

		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height),

				1) - 3;

	}



	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);

	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);

	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height);

	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height);



	// TODO: take the max between luma, chroma chunk size?

	// okay for now, as we are setting chunk_bytes to 8kb anyways

	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb

	if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb

		rq_regs->drq_expansion_mode = 0;

	} else {

		rq_regs->drq_expansion_mode = 2;
@@ -218,9 +218,9 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, 
	rq_regs->mrq_expansion_mode = 1;

	rq_regs->crq_expansion_mode = 1;



	if (rq_param.yuv420) {

		if ((double) rq_param.misc.rq_l.stored_swath_bytes

				/ (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {

	if (rq_param->yuv420) {

		if ((double) rq_param->misc.rq_l.stored_swath_bytes

				/ (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) {

			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma

		} else {

			detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
@@ -233,7 +233,7 @@ static void extract_rq_regs(struct display_mode_lib *mode_lib, 


static void handle_det_buf_split(struct display_mode_lib *mode_lib,

		display_rq_params_st *rq_param,

		const display_pipe_source_params_st pipe_src_param)

		const display_pipe_source_params_st *pipe_src_param)

{

	unsigned int total_swath_bytes = 0;

	unsigned int swath_bytes_l = 0;
@@ -242,8 +242,8 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, 
	unsigned int full_swath_bytes_packed_c = 0;

	bool req128_l = false;

	bool req128_c = false;

	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);

	bool surf_vert = (pipe_src_param.source_scan == dm_vert);

	bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear);

	bool surf_vert = (pipe_src_param->source_scan == dm_vert);

	unsigned int log2_swath_height_l = 0;

	unsigned int log2_swath_height_c = 0;

	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
@@ -685,7 +685,7 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, 
		display_data_rq_sizing_params_st *rq_sizing_param,

		display_data_rq_dlg_params_st *rq_dlg_param,

		display_data_rq_misc_params_st *rq_misc_param,

		const display_pipe_source_params_st pipe_src_param,

		const display_pipe_source_params_st *pipe_src_param,

		bool is_chroma)

{

	bool mode_422 = false;
@@ -697,15 +697,15 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, 


	// TODO check if ppe apply for both luma and chroma in 422 case

	if (is_chroma) {

		vp_width = pipe_src_param.viewport_width_c / ppe;

		vp_height = pipe_src_param.viewport_height_c;

		data_pitch = pipe_src_param.data_pitch_c;

		meta_pitch = pipe_src_param.meta_pitch_c;

		vp_width = pipe_src_param->viewport_width_c / ppe;

		vp_height = pipe_src_param->viewport_height_c;

		data_pitch = pipe_src_param->data_pitch_c;

		meta_pitch = pipe_src_param->meta_pitch_c;

	} else {

		vp_width = pipe_src_param.viewport_width / ppe;

		vp_height = pipe_src_param.viewport_height;

		data_pitch = pipe_src_param.data_pitch;

		meta_pitch = pipe_src_param.meta_pitch;

		vp_width = pipe_src_param->viewport_width / ppe;

		vp_height = pipe_src_param->viewport_height;

		data_pitch = pipe_src_param->data_pitch;

		meta_pitch = pipe_src_param->meta_pitch;

	}



	rq_sizing_param->chunk_bytes = 8192;
@@ -728,21 +728,21 @@ static void get_surf_rq_param(struct display_mode_lib *mode_lib, 
			vp_height,

			data_pitch,

			meta_pitch,

			pipe_src_param.source_format,

			pipe_src_param.sw_mode,

			pipe_src_param.macro_tile_size,

			pipe_src_param.source_scan,

			pipe_src_param->source_format,

			pipe_src_param->sw_mode,

			pipe_src_param->macro_tile_size,

			pipe_src_param->source_scan,

			is_chroma);

}



static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,

		display_rq_params_st *rq_param,

		const display_pipe_source_params_st pipe_src_param)

		const display_pipe_source_params_st *pipe_src_param)

{

	// get param for luma surface

	rq_param->yuv420 = pipe_src_param.source_format == dm_420_8

			|| pipe_src_param.source_format == dm_420_10;

	rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;

	rq_param->yuv420 = pipe_src_param->source_format == dm_420_8

			|| pipe_src_param->source_format == dm_420_10;

	rq_param->yuv420_10bpc = pipe_src_param->source_format == dm_420_10;



	get_surf_rq_param(mode_lib,

			&(rq_param->sizing.rq_l),
@@ -751,7 +751,7 @@ static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 
			pipe_src_param,

			0);



	if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {

	if (is_dual_plane((enum source_format_class)(pipe_src_param->source_format))) {

		// get param for chroma surface

		get_surf_rq_param(mode_lib,

				&(rq_param->sizing.rq_c),
@@ -773,8 +773,8 @@ void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 
	display_rq_params_st rq_param = {0};



	memset(rq_regs, 0, sizeof(*rq_regs));

	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param->src);

	extract_rq_regs(mode_lib, rq_regs, rq_param);

	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, &pipe_param->src);

	extract_rq_regs(mode_lib, rq_regs, &rq_param);



	print__rq_regs_st(mode_lib, rq_regs);

}
@@ -787,8 +787,8 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
		const unsigned int pipe_idx,

		display_dlg_regs_st *disp_dlg_regs,

		display_ttu_regs_st *disp_ttu_regs,

		const display_rq_dlg_params_st rq_dlg_param,

		const display_dlg_sys_params_st dlg_sys_param,

		const display_rq_dlg_params_st *rq_dlg_param,

		const display_dlg_sys_params_st *dlg_sys_param,

		const bool cstate_en,

		const bool pstate_en)

{
@@ -935,7 +935,7 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
			* (double) ref_freq_to_pix_freq);

	ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));



	min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;

	min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz;

	t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);

	min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
@@ -996,20 +996,20 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
//     vinit_bot_l     = scl.vinit_bot;

//     vinit_bot_c     = scl.vinit_bot_c;



//    unsigned int swath_height_l                 = rq_dlg_param.rq_l.swath_height;

	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;

//    unsigned int dpte_bytes_per_row_ub_l        = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;

	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;

//    unsigned int meta_pte_bytes_per_frame_ub_l  = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;

//    unsigned int meta_bytes_per_row_ub_l        = rq_dlg_param.rq_l.meta_bytes_per_row_ub;

//    unsigned int swath_height_l                 = rq_dlg_param->rq_l.swath_height;

	swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub;

//    unsigned int dpte_bytes_per_row_ub_l        = rq_dlg_param->rq_l.dpte_bytes_per_row_ub;

	dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub;

//    unsigned int meta_pte_bytes_per_frame_ub_l  = rq_dlg_param->rq_l.meta_pte_bytes_per_frame_ub;

//    unsigned int meta_bytes_per_row_ub_l        = rq_dlg_param->rq_l.meta_bytes_per_row_ub;



//    unsigned int swath_height_c                 = rq_dlg_param.rq_c.swath_height;

	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;

	//   dpte_bytes_per_row_ub_c        = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;

	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;

//    unsigned int swath_height_c                 = rq_dlg_param->rq_c.swath_height;

	swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub;

	//   dpte_bytes_per_row_ub_c        = rq_dlg_param->rq_c.dpte_bytes_per_row_ub;

	dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub;



	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;

	meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;

	meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub;

	meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub;

	vupdate_offset = dst->vupdate_offset;

	vupdate_width = dst->vupdate_width;

	vready_offset = dst->vready_offset;
@@ -1138,16 +1138,16 @@ static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 
	dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);



	// Active

	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;

	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;

	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;

	meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;

	req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub;

	req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub;

	meta_row_height_l = rq_dlg_param->rq_l.meta_row_height;

	meta_row_height_c = rq_dlg_param->rq_c.meta_row_height;

	swath_width_pixels_ub_l = 0;

	swath_width_pixels_ub_c = 0;

	scaler_rec_in_width_l = 0;

	scaler_rec_in_width_c = 0;

	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;

	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;

	dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height;

	dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height;



	if (mode_422) {

		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
@@ -1585,15 +1585,15 @@ void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 
	// system parameter calculation done



	dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);

	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src);

	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe.src);

	dml20v2_rq_dlg_get_dlg_params(mode_lib,

			e2e_pipe_param,

			num_pipes,

			pipe_idx,

			dlg_regs,

			ttu_regs,

			rq_param.dlg,

			dlg_sys_param,

			&rq_param.dlg,

			&dlg_sys_param,

			cstate_en,

			pstate_en);

	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

+34 −34

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

+17 −17

File changed.

Preview size limit exceeded, changes collapsed.