Commit 7588a893 authored by Baochen Qiang's avatar Baochen Qiang Committed by Jeff Johnson
Browse files

wifi: ath12k: fix GCC_GCC_PCIE_HOT_RST definition for WCN7850 



GCC_GCC_PCIE_HOT_RST is wrongly defined for WCN7850, causing kernel crash
on some specific platforms.

Since this register is divergent for WCN7850 and QCN9274, move it to
register table to allow different definitions. Then correct the register
address for WCN7850 to fix this issue.

Note IPQ5332 is not affected as it is not PCIe based device.

Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3

Signed-off-by: default avatarBaochen Qiang <quic_bqiang@quicinc.com>
Reviewed-by: default avatarVasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Reported-by: default avatarParth Pancholi <parth.pancholi@toradex.com>
Closes: https://lore.kernel.org/all/86899b2235a59c9134603beebe08f2bb0b244ea0.camel@gmail.com


Fixes: d8899132 ("wifi: ath12k: driver for Qualcomm Wi-Fi 7 devices")
Tested-by: default avatarParth Pancholi <parth.pancholi@toradex.com>
Link: https://patch.msgid.link/20250523-ath12k-wrong-global-reset-addr-v1-1-3b06eb556196@quicinc.com


Signed-off-by: default avatarJeff Johnson <jeff.johnson@oss.qualcomm.com>
parent b0d226a6

drivers/net/wireless/ath/ath12k/hw.c

+6 −0
Original line number Diff line number Diff line
@@ -951,6 +951,8 @@ static const struct ath12k_hw_regs qcn9274_v1_regs = { 
	.hal_umac_ce0_dest_reg_base = 0x01b81000,

	.hal_umac_ce1_src_reg_base = 0x01b82000,

	.hal_umac_ce1_dest_reg_base = 0x01b83000,



	.gcc_gcc_pcie_hot_rst = 0x1e38338,

};



static const struct ath12k_hw_regs qcn9274_v2_regs = {
@@ -1042,6 +1044,8 @@ static const struct ath12k_hw_regs qcn9274_v2_regs = { 
	.hal_umac_ce0_dest_reg_base = 0x01b81000,

	.hal_umac_ce1_src_reg_base = 0x01b82000,

	.hal_umac_ce1_dest_reg_base = 0x01b83000,



	.gcc_gcc_pcie_hot_rst = 0x1e38338,

};



static const struct ath12k_hw_regs ipq5332_regs = {
@@ -1215,6 +1219,8 @@ static const struct ath12k_hw_regs wcn7850_regs = { 
	.hal_umac_ce0_dest_reg_base = 0x01b81000,

	.hal_umac_ce1_src_reg_base = 0x01b82000,

	.hal_umac_ce1_dest_reg_base = 0x01b83000,



	.gcc_gcc_pcie_hot_rst = 0x1e40304,

};



static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = {

drivers/net/wireless/ath/ath12k/hw.h

+2 −0
Original line number Diff line number Diff line
@@ -375,6 +375,8 @@ struct ath12k_hw_regs { 
	u32 hal_reo_cmd_ring_base;



	u32 hal_reo_status_ring_base;



	u32 gcc_gcc_pcie_hot_rst;

};



static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type)

drivers/net/wireless/ath/ath12k/pci.c

+3 −3
Original line number Diff line number Diff line
@@ -292,10 +292,10 @@ static void ath12k_pci_enable_ltssm(struct ath12k_base *ab) 


	ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val);



	val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);

	val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab));

	val |= GCC_GCC_PCIE_HOT_RST_VAL;

	ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val);

	val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);

	ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST(ab), val);

	val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab));



	ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);

drivers/net/wireless/ath/ath12k/pci.h

+3 −1
Original line number Diff line number Diff line
@@ -28,7 +28,9 @@ 
#define PCIE_PCIE_PARF_LTSSM			0x1e081b0

#define PARM_LTSSM_VALUE			0x111



#define GCC_GCC_PCIE_HOT_RST			0x1e38338

#define GCC_GCC_PCIE_HOT_RST(ab) \

	((ab)->hw_params->regs->gcc_gcc_pcie_hot_rst)



#define GCC_GCC_PCIE_HOT_RST_VAL		0x10



#define PCIE_PCIE_INT_ALL_CLEAR			0x1e08228