Commit 75ea9cf9 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

Merge tag 'renesas-r9a09g047-dt-binding-defs-tag2' into renesas-pinctrl-for-v6.14 

Renesas RZ/G3E Pin Control DT Binding Definitions

Pin control DT bindings and binding definitions for the Renesas RZ/G3E
(R9A09G047) SoC, shared by driver and DT source files.
parents 0ce66380 5c7fb203

Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

+9 −6
Original line number Diff line number Diff line
@@ -4,19 +4,22 @@ 
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)

title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation

  and control of clock signals for the IP modules, generation and control of resets,

  and control over booting, low power consumption and power supply domains.

  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles

  generation and control of clock signals for the IP modules, generation and

  control of resets, and control over booting, low power consumption and power

  supply domains.



properties:

  compatible:

    const: renesas,r9a09g057-cpg

    enum:

      - renesas,r9a09g047-cpg # RZ/G3E

      - renesas,r9a09g057-cpg # RZ/V2H



  reg:

    maxItems: 1
@@ -37,7 +40,7 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,

        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number.  The module number is calculated as the CLKON register

        offset index multiplied by 16, plus the actual bit in the register

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

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Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ properties: 
              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five

              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}

              - renesas,r9a08g045-pinctrl # RZ/G3S

              - renesas,r9a09g047-pinctrl # RZ/G3E

              - renesas,r9a09g057-pinctrl # RZ/V2H(P)



      - items:
@@ -125,7 +126,7 @@ additionalProperties: 
        drive-push-pull: true

        renesas,output-impedance:

          description:

            Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this

            Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this

            property corresponds to register bit values that can be set in the PFC_IOLH_mn

            register, which adjusts the drive strength value and is pin-dependent.

          $ref: /schemas/types.yaml#/definitions/uint32
@@ -142,7 +143,9 @@ allOf: 
      properties:

        compatible:

          contains:

            const: renesas,r9a09g057-pinctrl

            enum:

              - renesas,r9a09g047-pinctrl

              - renesas,r9a09g057-pinctrl

    then:

      properties:

        resets:

Documentation/devicetree/bindings/soc/renesas/renesas.yaml

+17 −0
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@@ -525,6 +525,23 @@ properties: 
              - renesas,rzv2mevk2   # RZ/V2M Eval Board v2.0

          - const: renesas,r9a09g011



      - description: RZ/G3E (R9A09G047)

        items:

          - enum:

              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK

          - enum:

              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)

          - enum:

              - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)

              - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)

              - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)

              - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

              - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)

              - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)

              - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)

              - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)

          - const: renesas,r9a09g047



      - description: RZ/V2H(P) (R9A09G057)

        items:

          - enum:

include/dt-bindings/clock/renesas,r9a09g047-cpg.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

 *

 * Copyright (C) 2024 Renesas Electronics Corp.

 */

#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__

#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__



#include <dt-bindings/clock/renesas-cpg-mssr.h>



/* Core Clock list */

#define R9A09G047_SYS_0_PCLK			0

#define R9A09G047_CA55_0_CORECLK0		1

#define R9A09G047_CA55_0_CORECLK1		2

#define R9A09G047_CA55_0_CORECLK2		3

#define R9A09G047_CA55_0_CORECLK3		4

#define R9A09G047_CA55_0_PERIPHCLK		5

#define R9A09G047_CM33_CLK0			6

#define R9A09G047_CST_0_SWCLKTCK		7

#define R9A09G047_IOTOP_0_SHCLK			8



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */

include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * This header provides constants for Renesas RZ/G3E family pinctrl bindings.

 *

 * Copyright (C) 2024 Renesas Electronics Corp.

 *

 */



#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__

#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__



#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>



/* RZG3E_Px = Offset address of PFC_P_mn  - 0x20 */

#define RZG3E_P0	0

#define RZG3E_P1	1

#define RZG3E_P2	2

#define RZG3E_P3	3

#define RZG3E_P4	4

#define RZG3E_P5	5

#define RZG3E_P6	6

#define RZG3E_P7	7

#define RZG3E_P8	8

#define RZG3E_PA	10

#define RZG3E_PB	11

#define RZG3E_PC	12

#define RZG3E_PD	13

#define RZG3E_PE	14

#define RZG3E_PF	15

#define RZG3E_PG	16

#define RZG3E_PH	17

#define RZG3E_PJ	19

#define RZG3E_PK	20

#define RZG3E_PL	21

#define RZG3E_PM	22

#define RZG3E_PS	28



#define RZG3E_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)

#define RZG3E_GPIO(port, pin)		RZG2L_GPIO(RZG3E_P##port, pin)



#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */