Commit 75f9a484 authored by Brian Ruley's avatar Brian Ruley Committed by Russell King (Oracle)
Browse files

ARM: 9472/1: fix race condition on PG_dcache_clean in __sync_icache_dcache() 

This bug was already discovered and fixed for arm64 in
commit 588a513d ("arm64: Fix race condition on PG_dcache_clean in
__sync_icache_dcache()").

Verified with added instrumentation to track dcache flushes in a ring
buffer, as shown by the (distilled) output:

  kernel: SIGILL at b6b80ac0 cpu 1 pid 32663 linux_pte=8eff659f
          hw_pte=8eff6e7e young=1 exec=1
  kernel: dcache flush START   cpu0 pfn=8eff6 ts=48629557020154
  kernel: dcache flush SKIPPED cpu1 pfn=8eff6 ts=48629557020154
  kernel: dcache flush FINISH  cpu0 pfn=8eff6 ts=48629557036154
  audisp-syslog: comm="journalctl" exe="/usr/bin/journalctl" sig=4 [...]

Discussions in the mailing list mentioned that arch/arm is also affected
but the fix was never applied to it [1][2]. Apply the change now, since
the race condition can cause sporadic SIGILL's and SEGV's especially
while under high memory pressure.

Link: https://lore.kernel.org/all/adzMOdySgMIePcue@willie-the-truck [1]
Link: https://lore.kernel.org/all/20210514095001.13236-1-catalin.marinas@arm.com

 [2]
Signed-off-by: default avatarBrian Ruley <brian.ruley@gehealthcare.com>
Reviewed-by: default avatarWill Deacon <will@kernel.org>
Cc: <stable@vger.kernel.org>
Fixes: 6012191a ("ARM: 6380/1: Introduce __sync_icache_dcache() for VIPT caches")
Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
parent 6de23f81

arch/arm/mm/flush.c

+3 −1
Original line number Diff line number Diff line
@@ -304,8 +304,10 @@ void __sync_icache_dcache(pte_t pteval) 
	else

		mapping = NULL;



	if (!test_and_set_bit(PG_dcache_clean, &folio->flags.f))

	if (!test_bit(PG_dcache_clean, &folio->flags.f)) {

		__flush_dcache_folio(mapping, folio);

		set_bit(PG_dcache_clean, &folio->flags.f);

	}



	if (pte_exec(pteval))

		__flush_icache_all();