Commit 760632fa authored by Alexandre Demers's avatar Alexandre Demers Committed by Alex Deucher
Browse files

drm/amdgpu: fix SI's GB_ADDR_CONFIG_GOLDEN values and wire up sid.h in GFX6 



By wiring up sid.h in GFX6, we end up with a few duplicated defines such as
the golden registers. Let's clean this up.

[TAHITI,VERDE, HAINAN]_GB_ADDR_CONFIG_GOLDEN were defined both in sid.h
and under si_enums.h, with different values. Keep the values used under radeon
and move them under gfx_v6_0.c where they are used (as it is done under cik)

Signed-off-by: default avatarAlexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 20fb56df

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+13 −2
Original line number Diff line number Diff line
@@ -28,19 +28,30 @@ 
#include "amdgpu_gfx.h"

#include "amdgpu_ucode.h"

#include "clearstate_si.h"

#include "si.h"

#include "sid.h"



#include "bif/bif_3_0_d.h"

#include "bif/bif_3_0_sh_mask.h"



#include "oss/oss_1_0_d.h"

#include "oss/oss_1_0_sh_mask.h"



#include "gca/gfx_6_0_d.h"

#include "gca/gfx_6_0_sh_mask.h"

#include "gca/gfx_7_2_enum.h"



#include "gmc/gmc_6_0_d.h"

#include "gmc/gmc_6_0_sh_mask.h"



#include "dce/dce_6_0_d.h"

#include "dce/dce_6_0_sh_mask.h"

#include "gca/gfx_7_2_enum.h"



#include "si_enums.h"

#include "si.h"



#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003

#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002

#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001



static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);

static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/si_enums.h

+0 −6
Original line number Diff line number Diff line
@@ -128,8 +128,6 @@ 
#define SI_CRTC4_REGISTER_OFFSET                0x2c00

#define SI_CRTC5_REGISTER_OFFSET                0x2f00



#define DMA0_REGISTER_OFFSET 0x000

#define DMA1_REGISTER_OFFSET 0x200

#define ES_AND_GS_AUTO       3

#define RADEON_PACKET_TYPE3  3

#define CE_PARTITION_BASE    3
@@ -161,10 +159,6 @@ 
#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90

#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D



#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003

#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x02010002

#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02011003



#define PACKET3(op, n)  ((RADEON_PACKET_TYPE3 << 30) |                  \

                         (((op) & 0xFF) << 8) |                         \

                         ((n) & 0x3FFF) << 16)

drivers/gpu/drm/amd/amdgpu/sid.h

+0 −4
Original line number Diff line number Diff line
@@ -26,10 +26,6 @@ 


#define TAHITI_RB_BITMAP_WIDTH_PER_SH  2



#define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003

#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002

#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001



#define SI_MAX_SH_GPRS		 	256

#define SI_MAX_TEMP_GPRS         	16

#define SI_MAX_SH_THREADS        	256