Commit 76120b3a authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro 



The format of the port width field in the DDI_BUF_CTL and the
TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
x3 lane mode for HDMI FRL has a different encoding in the two registers.
To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.

Cc: <stable@vger.kernel.org> # v6.5+
Fixes: b66a8aba ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-2-imre.deak@intel.com
parent bccb18c5

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -805,8 +805,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 
		/* select data lane width */

		tmp = intel_de_read(display,

				    TRANS_DDI_FUNC_CTL(display, dsi_trans));

		tmp &= ~DDI_PORT_WIDTH_MASK;

		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);

		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;

		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);



		/* select input pipe */

		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;