Commit 762ef94b authored by Frank Li's avatar Frank Li Committed by Lorenzo Pieralisi
Browse files

PCI: layerscape(ep): Rename pf_* as pf_lut_* 

'pf' and 'lut' are two different acronyms describing the same
thing, basically it is a MMIO base address plus an offset.

Rename them to avoid duplicate pf_* and lut_* naming schemes in the
driver.

Link: https://lore.kernel.org/r/20231204160829.2498703-4-Frank.Li@nxp.com


Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: default avatarRoy Zang <Roy.Zang@nxp.com>
parent 6f8a41ba

drivers/pci/controller/dwc/pci-layerscape-ep.c

+8 −8
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ struct ls_pcie_ep { 
	bool				big_endian;

};



static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset)

static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset)

{

	struct dw_pcie *pci = pcie->pci;
@@ -59,7 +59,7 @@ static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) 
		return ioread32(pci->dbi_base + offset);

}



static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)

static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)

{

	struct dw_pcie *pci = pcie->pci;
@@ -76,8 +76,8 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) 
	u32 val, cfg;

	u8 offset;



	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);

	ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);

	val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR);

	ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);



	if (!val)

		return IRQ_NONE;
@@ -96,9 +96,9 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) 
		dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);

		dw_pcie_dbi_ro_wr_dis(pci);



		cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);

		cfg = ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG);

		cfg |= PEX_PF0_CFG_READY;

		ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);

		ls_pcie_pf_lut_writel(pcie, PEX_PF0_CONFIG, cfg);

		dw_pcie_ep_linkup(&pci->ep);



		dev_dbg(pci->dev, "Link up\n");
@@ -130,10 +130,10 @@ static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie, 
	}



	/* Enable interrupts */

	val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER);

	val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_IER);

	val |=  PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE |

		PEX_PF0_PME_MES_IER_LUDIE;

	ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);

	ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);



	return 0;

}

drivers/pci/controller/dwc/pci-layerscape.c

+17 −17
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ 
#define PCIE_IATU_NUM		6



struct ls_pcie_drvdata {

	const u32 pf_off;

	const u32 pf_lut_off;

	const struct dw_pcie_host_ops *ops;

	int (*exit_from_l2)(struct dw_pcie_rp *pp);

	bool scfg_support;
@@ -54,13 +54,13 @@ struct ls_pcie_drvdata { 
struct ls_pcie {

	struct dw_pcie *pci;

	const struct ls_pcie_drvdata *drvdata;

	void __iomem *pf_base;

	void __iomem *pf_lut_base;

	struct regmap *scfg;

	int index;

	bool big_endian;

};



#define ls_pcie_pf_readl_addr(addr)	ls_pcie_pf_readl(pcie, addr)

#define ls_pcie_pf_lut_readl_addr(addr)	ls_pcie_pf_lut_readl(pcie, addr)

#define to_ls_pcie(x)	dev_get_drvdata((x)->dev)



static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
@@ -101,20 +101,20 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) 
	iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);

}



static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off)

static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off)

{

	if (pcie->big_endian)

		return ioread32be(pcie->pf_base + off);

		return ioread32be(pcie->pf_lut_base + off);



	return ioread32(pcie->pf_base + off);

	return ioread32(pcie->pf_lut_base + off);

}



static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val)

static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val)

{

	if (pcie->big_endian)

		iowrite32be(val, pcie->pf_base + off);

		iowrite32be(val, pcie->pf_lut_base + off);

	else

		iowrite32(val, pcie->pf_base + off);

		iowrite32(val, pcie->pf_lut_base + off);

}



static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
@@ -124,11 +124,11 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) 
	u32 val;

	int ret;



	val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);

	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);

	val |= PF_MCR_PTOMR;

	ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);

	ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);



	ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,

	ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,

				 val, !(val & PF_MCR_PTOMR),

				 PCIE_PME_TO_L2_TIMEOUT_US/10,

				 PCIE_PME_TO_L2_TIMEOUT_US);
@@ -147,15 +147,15 @@ static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) 
	 * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link

	 * to exit L2 state.

	 */

	val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);

	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);

	val |= PF_MCR_EXL2S;

	ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);

	ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);



	/*

	 * L2 exit timeout of 10ms is not defined in the specifications,

	 * it was chosen based on empirical observations.

	 */

	ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,

	ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,

				 val, !(val & PF_MCR_EXL2S),

				 1000,

				 10000);
@@ -242,7 +242,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { 
};



static const struct ls_pcie_drvdata layerscape_drvdata = {

	.pf_off = 0xc0000,

	.pf_lut_off = 0xc0000,

	.pm_support = true,

	.ops = &ls_pcie_host_ops,

	.exit_from_l2 = ls_pcie_exit_from_l2,
@@ -291,7 +291,7 @@ static int ls_pcie_probe(struct platform_device *pdev) 


	pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");



	pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off;

	pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off;



	if (pcie->drvdata->scfg_support) {

		pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg");