Commit 763e15d0 authored by Dave Jiang's avatar Dave Jiang
Browse files

Merge branch 'for-6.15/extended-linear-cache' into cxl-for-next2 

Add support for Extended Linear Cache for CXL. Add enumeration support
of the cache. Add MCE notification of the aliased memory address.
parents d781a452 516e5bd0

Documentation/ABI/stable/sysfs-devices-node

+6 −0
Original line number Diff line number Diff line
@@ -177,6 +177,12 @@ Description: 
		The cache write policy: 0 for write-back, 1 for write-through,

		other or unknown.



What:		/sys/devices/system/node/nodeX/memory_side_cache/indexY/address_mode

Date:		March 2025

Contact:	Dave Jiang <dave.jiang@intel.com>

Description:

		The address mode: 0 for reserved, 1 for extended-linear.



What:		/sys/devices/system/node/nodeX/x86/sgx_total_bytes

Date:		November 2021

Contact:	Jarkko Sakkinen <jarkko@kernel.org>

arch/x86/mm/pat/set_memory.c

+1 −0
Original line number Diff line number Diff line
@@ -2081,6 +2081,7 @@ int set_mce_nospec(unsigned long pfn) 
		pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn);

	return rc;

}

EXPORT_SYMBOL_GPL(set_mce_nospec);



/* Restore full speculative operation to the pfn. */

int clear_mce_nospec(unsigned long pfn)

drivers/acpi/numa/hmat.c

+44 −0
Original line number Diff line number Diff line
@@ -108,6 +108,45 @@ static struct memory_target *find_mem_target(unsigned int mem_pxm) 
	return NULL;

}



/**

 * hmat_get_extended_linear_cache_size - Retrieve the extended linear cache size

 * @backing_res: resource from the backing media

 * @nid: node id for the memory region

 * @cache_size: (Output) size of extended linear cache.

 *

 * Return: 0 on success. Errno on failure.

 *

 */

int hmat_get_extended_linear_cache_size(struct resource *backing_res, int nid,

					resource_size_t *cache_size)

{

	unsigned int pxm = node_to_pxm(nid);

	struct memory_target *target;

	struct target_cache *tcache;

	struct resource *res;



	target = find_mem_target(pxm);

	if (!target)

		return -ENOENT;



	list_for_each_entry(tcache, &target->caches, node) {

		if (tcache->cache_attrs.address_mode !=

				NODE_CACHE_ADDR_MODE_EXTENDED_LINEAR)

			continue;



		res = &target->memregions;

		if (!resource_contains(res, backing_res))

			continue;



		*cache_size = tcache->cache_attrs.size;

		return 0;

	}



	*cache_size = 0;

	return 0;

}

EXPORT_SYMBOL_NS_GPL(hmat_get_extended_linear_cache_size, "CXL");



static struct memory_target *acpi_find_genport_target(u32 uid)

{

	struct memory_target *target;
@@ -506,6 +545,11 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, 
	switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) {

	case ACPI_HMAT_CA_DIRECT_MAPPED:

		tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP;

		/* Extended Linear mode is only valid if cache is direct mapped */

		if (cache->address_mode == ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR) {

			tcache->cache_attrs.address_mode =

				NODE_CACHE_ADDR_MODE_EXTENDED_LINEAR;

		}

		break;

	case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING:

		tcache->cache_attrs.indexing = NODE_CACHE_INDEXED;

drivers/base/node.c

+2 −0
Original line number Diff line number Diff line
@@ -244,12 +244,14 @@ CACHE_ATTR(size, "%llu") 
CACHE_ATTR(line_size, "%u")

CACHE_ATTR(indexing, "%u")

CACHE_ATTR(write_policy, "%u")

CACHE_ATTR(address_mode, "%#x")



static struct attribute *cache_attrs[] = {

	&dev_attr_indexing.attr,

	&dev_attr_size.attr,

	&dev_attr_line_size.attr,

	&dev_attr_write_policy.attr,

	&dev_attr_address_mode.attr,

	NULL,

};

ATTRIBUTE_GROUPS(cache);

drivers/cxl/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -146,4 +146,8 @@ config CXL_REGION_INVALIDATION_TEST 
	  If unsure, or if this kernel is meant for production environments,

	  say N.



config CXL_MCE

	def_bool y

	depends on X86_MCE && MEMORY_FAILURE



endif