Commit 7654d51f authored by Aradhya Bhatia's avatar Aradhya Bhatia Committed by Tejas Upadhyay
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drm/xe/xe2hpg: Add Wa_16025250150



Add Wa_16025250150 for the Xe2_HPG (graphics version: 20.01) platforms.
It is a permanent workaround, and applicable on all the steppings.

Reviewed-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: default avatarAradhya Bhatia <aradhya.bhatia@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250325134421.1489416-1-aradhya.bhatia@intel.com


Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
parent 32cb8dc5
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+12 −0
Original line number Diff line number Diff line
@@ -392,6 +392,18 @@
#define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
#define   XEHP_LNESPARE				REG_BIT(19)

#define LSN_VC_REG2				XE_REG_MCR(0xb0c8)
#define   LSN_LNI_WGT_MASK			REG_GENMASK(31, 28)
#define   LSN_LNI_WGT(value)			REG_FIELD_PREP(LSN_LNI_WGT_MASK, value)
#define   LSN_LNE_WGT_MASK			REG_GENMASK(27, 24)
#define   LSN_LNE_WGT(value)			REG_FIELD_PREP(LSN_LNE_WGT_MASK, value)
#define   LSN_DIM_X_WGT_MASK			REG_GENMASK(23, 20)
#define   LSN_DIM_X_WGT(value)			REG_FIELD_PREP(LSN_DIM_X_WGT_MASK, value)
#define   LSN_DIM_Y_WGT_MASK			REG_GENMASK(19, 16)
#define   LSN_DIM_Y_WGT(value)			REG_FIELD_PREP(LSN_DIM_Y_WGT_MASK, value)
#define   LSN_DIM_Z_WGT_MASK			REG_GENMASK(15, 12)
#define   LSN_DIM_Z_WGT(value)			REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)

#define L3SQCREG2				XE_REG_MCR(0xb104)
#define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)

+12 −0
Original line number Diff line number Diff line
@@ -230,6 +230,18 @@ static const struct xe_rtp_entry_sr gt_was[] = {
	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
	},

	/* Xe2_HPG */

	{ XE_RTP_NAME("16025250150"),
	  XE_RTP_RULES(GRAPHICS_VERSION(2001)),
	  XE_RTP_ACTIONS(SET(LSN_VC_REG2,
			     LSN_LNI_WGT(1) |
			     LSN_LNE_WGT(1) |
			     LSN_DIM_X_WGT(1) |
			     LSN_DIM_Y_WGT(1) |
			     LSN_DIM_Z_WGT(1)))
	},

	/* Xe2_HPM */

	{ XE_RTP_NAME("16021867713"),