Unverified Commit 7668c637 authored by Sheetal's avatar Sheetal Committed by Mark Brown
Browse files

ASoC: tegra: ADMAIF: Add Tegra264 support 



Add Tegra264 I2S support with following changes:
- Add soc_data for Tegra264-specific variations
- Tegra264 supports 32 RX and 32 TX ADMAIF channels and each ADMAIF
  stream supports max 32 channels. To accommodate the change dais, CIF
  configuration API and driver components are updated.
- Register offsets and default values are updated to align with Tegra264.

Signed-off-by: default avatarSheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-5-sheetal@nvidia.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 35c0d1de

sound/soc/tegra/tegra210_admaif.c

+185 −38
Original line number Diff line number Diff line
@@ -25,12 +25,12 @@ 


#define CH_RX_REG(reg, id) CH_REG(admaif->soc_data->rx_base, reg, id)



#define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, tx_base, rx_base)		       \

#define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, tx_base, rx_base, cif_ctrl)	       \

	{ CH_REG(rx_base, TEGRA_ADMAIF_RX_INT_MASK, id), 0x00000001 },	       \

	{ CH_REG(rx_base, TEGRA_ADMAIF_CH_ACIF_RX_CTRL, id), 0x00007700 },     \

	{ CH_REG(rx_base, TEGRA_ADMAIF_CH_ACIF_RX_CTRL, id), cif_ctrl },     \

	{ CH_REG(rx_base, TEGRA_ADMAIF_RX_FIFO_CTRL, id), rx_ctrl },	       \

	{ CH_REG(tx_base, TEGRA_ADMAIF_TX_INT_MASK, id), 0x00000001 },	       \

	{ CH_REG(tx_base, TEGRA_ADMAIF_CH_ACIF_TX_CTRL, id), 0x00007700 },     \

	{ CH_REG(tx_base, TEGRA_ADMAIF_CH_ACIF_TX_CTRL, id), cif_ctrl },     \

	{ CH_REG(tx_base, TEGRA_ADMAIF_TX_FIFO_CTRL, id), tx_ctrl }



#define ADMAIF_REG_DEFAULTS(id, chip)					       \
@@ -38,7 +38,8 @@ 
		chip ## _ADMAIF_RX ## id ## _FIFO_CTRL_REG_DEFAULT,	       \

		chip ## _ADMAIF_TX ## id ## _FIFO_CTRL_REG_DEFAULT,	       \

		chip ## _ADMAIF_TX_BASE,				       \

		chip ## _ADMAIF_RX_BASE)

		chip ## _ADMAIF_RX_BASE,				       \

		chip ## _ADMAIF_CIF_REG_DEFAULT)



static const struct reg_default tegra186_admaif_reg_defaults[] = {

	{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA186_ADMAIF_GLOBAL_BASE), 0x00000003},
@@ -78,6 +79,42 @@ static const struct reg_default tegra210_admaif_reg_defaults[] = { 
	ADMAIF_REG_DEFAULTS(10, TEGRA210)

};



static const struct reg_default tegra264_admaif_reg_defaults[] = {

	{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA264_ADMAIF_GLOBAL_BASE), 0x00000003},

	ADMAIF_REG_DEFAULTS(1, TEGRA264),

	ADMAIF_REG_DEFAULTS(2, TEGRA264),

	ADMAIF_REG_DEFAULTS(3, TEGRA264),

	ADMAIF_REG_DEFAULTS(4, TEGRA264),

	ADMAIF_REG_DEFAULTS(5, TEGRA264),

	ADMAIF_REG_DEFAULTS(6, TEGRA264),

	ADMAIF_REG_DEFAULTS(7, TEGRA264),

	ADMAIF_REG_DEFAULTS(8, TEGRA264),

	ADMAIF_REG_DEFAULTS(9, TEGRA264),

	ADMAIF_REG_DEFAULTS(10, TEGRA264),

	ADMAIF_REG_DEFAULTS(11, TEGRA264),

	ADMAIF_REG_DEFAULTS(12, TEGRA264),

	ADMAIF_REG_DEFAULTS(13, TEGRA264),

	ADMAIF_REG_DEFAULTS(14, TEGRA264),

	ADMAIF_REG_DEFAULTS(15, TEGRA264),

	ADMAIF_REG_DEFAULTS(16, TEGRA264),

	ADMAIF_REG_DEFAULTS(17, TEGRA264),

	ADMAIF_REG_DEFAULTS(18, TEGRA264),

	ADMAIF_REG_DEFAULTS(19, TEGRA264),

	ADMAIF_REG_DEFAULTS(20, TEGRA264),

	ADMAIF_REG_DEFAULTS(21, TEGRA264),

	ADMAIF_REG_DEFAULTS(22, TEGRA264),

	ADMAIF_REG_DEFAULTS(23, TEGRA264),

	ADMAIF_REG_DEFAULTS(24, TEGRA264),

	ADMAIF_REG_DEFAULTS(25, TEGRA264),

	ADMAIF_REG_DEFAULTS(26, TEGRA264),

	ADMAIF_REG_DEFAULTS(27, TEGRA264),

	ADMAIF_REG_DEFAULTS(28, TEGRA264),

	ADMAIF_REG_DEFAULTS(29, TEGRA264),

	ADMAIF_REG_DEFAULTS(30, TEGRA264),

	ADMAIF_REG_DEFAULTS(31, TEGRA264),

	ADMAIF_REG_DEFAULTS(32, TEGRA264)

};



static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)

{

	struct tegra_admaif *admaif = dev_get_drvdata(dev);
@@ -220,6 +257,19 @@ static const struct regmap_config tegra186_admaif_regmap_config = { 
	.cache_type		= REGCACHE_FLAT,

};



static const struct regmap_config tegra264_admaif_regmap_config = {

	.reg_bits		= 32,

	.reg_stride		= 4,

	.val_bits		= 32,

	.max_register		= TEGRA264_ADMAIF_LAST_REG,

	.writeable_reg		= tegra_admaif_wr_reg,

	.readable_reg		= tegra_admaif_rd_reg,

	.volatile_reg		= tegra_admaif_volatile_reg,

	.reg_defaults		= tegra264_admaif_reg_defaults,

	.num_reg_defaults	= TEGRA264_ADMAIF_CHANNEL_COUNT * 6 + 1,

	.cache_type		= REGCACHE_FLAT,

};



static int tegra_admaif_runtime_suspend(struct device *dev)

{

	struct tegra_admaif *admaif = dev_get_drvdata(dev);
@@ -330,6 +380,9 @@ static int tegra_admaif_hw_params(struct snd_pcm_substream *substream, 


	tegra_admaif_set_pack_mode(admaif->regmap, reg, valid_bit);



	if (admaif->soc_data->max_stream_ch == TEGRA264_ADMAIF_MAX_CHANNEL)

		tegra264_set_cif(admaif->regmap, reg, &cif_conf);

	else

		tegra_set_cif(admaif->regmap, reg, &cif_conf);



	return 0;
@@ -571,13 +624,13 @@ static const struct snd_soc_dai_ops tegra_admaif_dai_ops = { 
	.prepare	= tegra_admaif_prepare,

};



#define DAI(dai_name)					\

#define DAI(dai_name, channel)					\

	{							\

		.name = dai_name,				\

		.playback = {					\

			.stream_name = dai_name " Playback",	\

			.channels_min = 1,			\

			.channels_max = 16,			\

			.channels_max = channel,		\

			.rates = SNDRV_PCM_RATE_8000_192000,	\

			.formats = SNDRV_PCM_FMTBIT_S8 |	\

				SNDRV_PCM_FMTBIT_S16_LE |	\
@@ -587,7 +640,7 @@ static const struct snd_soc_dai_ops tegra_admaif_dai_ops = { 
		.capture = {					\

			.stream_name = dai_name " Capture",	\

			.channels_min = 1,			\

			.channels_max = 16,			\

			.channels_max = channel,		\

			.rates = SNDRV_PCM_RATE_8000_192000,	\

			.formats = SNDRV_PCM_FMTBIT_S8 |	\

				SNDRV_PCM_FMTBIT_S16_LE |	\
@@ -598,39 +651,74 @@ static const struct snd_soc_dai_ops tegra_admaif_dai_ops = { 
	}



static struct snd_soc_dai_driver tegra210_admaif_cmpnt_dais[] = {

	DAI("ADMAIF1"),

	DAI("ADMAIF2"),

	DAI("ADMAIF3"),

	DAI("ADMAIF4"),

	DAI("ADMAIF5"),

	DAI("ADMAIF6"),

	DAI("ADMAIF7"),

	DAI("ADMAIF8"),

	DAI("ADMAIF9"),

	DAI("ADMAIF10"),

	DAI("ADMAIF1", TEGRA210_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF2", TEGRA210_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF3", TEGRA210_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF4", TEGRA210_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF5", TEGRA210_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF6", TEGRA210_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF7", TEGRA210_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF8", TEGRA210_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF9", TEGRA210_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF10", TEGRA210_ADMAIF_MAX_CHANNEL),

};



static struct snd_soc_dai_driver tegra186_admaif_cmpnt_dais[] = {

	DAI("ADMAIF1"),

	DAI("ADMAIF2"),

	DAI("ADMAIF3"),

	DAI("ADMAIF4"),

	DAI("ADMAIF5"),

	DAI("ADMAIF6"),

	DAI("ADMAIF7"),

	DAI("ADMAIF8"),

	DAI("ADMAIF9"),

	DAI("ADMAIF10"),

	DAI("ADMAIF11"),

	DAI("ADMAIF12"),

	DAI("ADMAIF13"),

	DAI("ADMAIF14"),

	DAI("ADMAIF15"),

	DAI("ADMAIF16"),

	DAI("ADMAIF17"),

	DAI("ADMAIF18"),

	DAI("ADMAIF19"),

	DAI("ADMAIF20"),

	DAI("ADMAIF1", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF2", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF3", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF4", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF5", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF6", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF7", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF8", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF9", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF10", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF11", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF12", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF13", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF14", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF15", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF16", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF17", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF18", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF19", TEGRA186_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF20", TEGRA186_ADMAIF_MAX_CHANNEL),

};



static struct snd_soc_dai_driver tegra264_admaif_cmpnt_dais[] = {

	DAI("ADMAIF1", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF2", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF3", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF4", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF5", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF6", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF7", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF8", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF9", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF10", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF11", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF12", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF13", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF14", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF15", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF16", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF17", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF18", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF19", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF20", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF21", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF22", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF23", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF24", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF25", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF26", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF27", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF28", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF29", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF30", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF31", TEGRA264_ADMAIF_MAX_CHANNEL),

	DAI("ADMAIF32", TEGRA264_ADMAIF_MAX_CHANNEL),

};



static const char * const tegra_admaif_stereo_conv_text[] = {
@@ -710,6 +798,41 @@ static struct snd_kcontrol_new tegra186_admaif_controls[] = { 
	TEGRA_ADMAIF_CIF_CTRL(20),

};



static struct snd_kcontrol_new tegra264_admaif_controls[] = {

	TEGRA_ADMAIF_CIF_CTRL(1),

	TEGRA_ADMAIF_CIF_CTRL(2),

	TEGRA_ADMAIF_CIF_CTRL(3),

	TEGRA_ADMAIF_CIF_CTRL(4),

	TEGRA_ADMAIF_CIF_CTRL(5),

	TEGRA_ADMAIF_CIF_CTRL(6),

	TEGRA_ADMAIF_CIF_CTRL(7),

	TEGRA_ADMAIF_CIF_CTRL(8),

	TEGRA_ADMAIF_CIF_CTRL(9),

	TEGRA_ADMAIF_CIF_CTRL(10),

	TEGRA_ADMAIF_CIF_CTRL(11),

	TEGRA_ADMAIF_CIF_CTRL(12),

	TEGRA_ADMAIF_CIF_CTRL(13),

	TEGRA_ADMAIF_CIF_CTRL(14),

	TEGRA_ADMAIF_CIF_CTRL(15),

	TEGRA_ADMAIF_CIF_CTRL(16),

	TEGRA_ADMAIF_CIF_CTRL(17),

	TEGRA_ADMAIF_CIF_CTRL(18),

	TEGRA_ADMAIF_CIF_CTRL(19),

	TEGRA_ADMAIF_CIF_CTRL(20),

	TEGRA_ADMAIF_CIF_CTRL(21),

	TEGRA_ADMAIF_CIF_CTRL(22),

	TEGRA_ADMAIF_CIF_CTRL(23),

	TEGRA_ADMAIF_CIF_CTRL(24),

	TEGRA_ADMAIF_CIF_CTRL(25),

	TEGRA_ADMAIF_CIF_CTRL(26),

	TEGRA_ADMAIF_CIF_CTRL(27),

	TEGRA_ADMAIF_CIF_CTRL(28),

	TEGRA_ADMAIF_CIF_CTRL(29),

	TEGRA_ADMAIF_CIF_CTRL(30),

	TEGRA_ADMAIF_CIF_CTRL(31),

	TEGRA_ADMAIF_CIF_CTRL(32),

};



static const struct snd_soc_component_driver tegra210_admaif_cmpnt = {

	.controls		= tegra210_admaif_controls,

	.num_controls		= ARRAY_SIZE(tegra210_admaif_controls),
@@ -730,8 +853,19 @@ static const struct snd_soc_component_driver tegra186_admaif_cmpnt = { 
	.pointer		= tegra_pcm_pointer,

};



static const struct snd_soc_component_driver tegra264_admaif_cmpnt = {

	.controls		= tegra264_admaif_controls,

	.num_controls		= ARRAY_SIZE(tegra264_admaif_controls),

	.pcm_construct		= tegra_pcm_construct,

	.open			= tegra_pcm_open,

	.close			= tegra_pcm_close,

	.hw_params		= tegra_pcm_hw_params,

	.pointer		= tegra_pcm_pointer,

};



static const struct tegra_admaif_soc_data soc_data_tegra210 = {

	.num_ch		= TEGRA210_ADMAIF_CHANNEL_COUNT,

	.max_stream_ch	= TEGRA210_ADMAIF_MAX_CHANNEL,

	.cmpnt		= &tegra210_admaif_cmpnt,

	.dais		= tegra210_admaif_cmpnt_dais,

	.regmap_conf	= &tegra210_admaif_regmap_config,
@@ -742,6 +876,7 @@ static const struct tegra_admaif_soc_data soc_data_tegra210 = { 


static const struct tegra_admaif_soc_data soc_data_tegra186 = {

	.num_ch		= TEGRA186_ADMAIF_CHANNEL_COUNT,

	.max_stream_ch	= TEGRA186_ADMAIF_MAX_CHANNEL,

	.cmpnt		= &tegra186_admaif_cmpnt,

	.dais		= tegra186_admaif_cmpnt_dais,

	.regmap_conf	= &tegra186_admaif_regmap_config,
@@ -750,9 +885,21 @@ static const struct tegra_admaif_soc_data soc_data_tegra186 = { 
	.rx_base	= TEGRA186_ADMAIF_RX_BASE,

};



static const struct tegra_admaif_soc_data soc_data_tegra264 = {

	.num_ch		= TEGRA264_ADMAIF_CHANNEL_COUNT,

	.max_stream_ch	= TEGRA264_ADMAIF_MAX_CHANNEL,

	.cmpnt		= &tegra264_admaif_cmpnt,

	.dais		= tegra264_admaif_cmpnt_dais,

	.regmap_conf	= &tegra264_admaif_regmap_config,

	.global_base	= TEGRA264_ADMAIF_GLOBAL_BASE,

	.tx_base	= TEGRA264_ADMAIF_TX_BASE,

	.rx_base	= TEGRA264_ADMAIF_RX_BASE,

};



static const struct of_device_id tegra_admaif_of_match[] = {

	{ .compatible = "nvidia,tegra210-admaif", .data = &soc_data_tegra210 },

	{ .compatible = "nvidia,tegra186-admaif", .data = &soc_data_tegra186 },

	{ .compatible = "nvidia,tegra264-admaif", .data = &soc_data_tegra264 },

	{},

};

MODULE_DEVICE_TABLE(of, tegra_admaif_of_match);

sound/soc/tegra/tegra210_admaif.h

+78 −0
Original line number Diff line number Diff line
@@ -16,12 +16,21 @@ 
#define TEGRA210_ADMAIF_RX_BASE				0x0

#define TEGRA210_ADMAIF_TX_BASE				0x300

#define TEGRA210_ADMAIF_GLOBAL_BASE			0x700

#define TEGRA210_ADMAIF_MAX_CHANNEL			16

/* Tegra186 specific */

#define TEGRA186_ADMAIF_LAST_REG			0xd5f

#define TEGRA186_ADMAIF_CHANNEL_COUNT			20

#define TEGRA186_ADMAIF_RX_BASE				0x0

#define TEGRA186_ADMAIF_TX_BASE				0x500

#define TEGRA186_ADMAIF_GLOBAL_BASE			0xd00

#define TEGRA186_ADMAIF_MAX_CHANNEL			16

/* Tegra264 specific */

#define TEGRA264_ADMAIF_LAST_REG			0x205f

#define TEGRA264_ADMAIF_CHANNEL_COUNT			32

#define TEGRA264_ADMAIF_RX_BASE				0x0

#define TEGRA264_ADMAIF_TX_BASE				0x1000

#define TEGRA264_ADMAIF_GLOBAL_BASE			0x2000

#define TEGRA264_ADMAIF_MAX_CHANNEL			32

/* Global registers */

#define TEGRA_ADMAIF_GLOBAL_ENABLE			0x0

#define TEGRA_ADMAIF_GLOBAL_CG_0			0x8
@@ -66,6 +75,7 @@ 
#define SW_RESET_MASK					1

#define SW_RESET					1

/* Default values - Tegra210 */

#define TEGRA210_ADMAIF_CIF_REG_DEFAULT			0x00007700

#define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT	0x00000300

#define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT	0x00000304

#define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT	0x00000208
@@ -87,6 +97,7 @@ 
#define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT	0x0180021a

#define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT	0x0180021d

/* Default values - Tegra186 */

#define TEGRA186_ADMAIF_CIF_REG_DEFAULT			0x00007700

#define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT	0x00000300

#define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT	0x00000304

#define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT	0x00000308
@@ -127,6 +138,72 @@ 
#define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT	0x01800237

#define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT	0x0180023a

#define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT	0x0180023d

/* Default values - Tegra264 */

#define TEGRA264_ADMAIF_CIF_REG_DEFAULT			0x00003f00

#define TEGRA264_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT	0x00000200

#define TEGRA264_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT	0x00000203

#define TEGRA264_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT	0x00000206

#define TEGRA264_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT	0x00000209

#define TEGRA264_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT	0x0000020c

#define TEGRA264_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT	0x0000020f

#define TEGRA264_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT	0x00000212

#define TEGRA264_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT	0x00000215

#define TEGRA264_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT	0x00000218

#define TEGRA264_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT	0x0000021b

#define TEGRA264_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT	0x0000021e

#define TEGRA264_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT	0x00000221

#define TEGRA264_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT	0x00000224

#define TEGRA264_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT	0x00000227

#define TEGRA264_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT	0x0000022a

#define TEGRA264_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT	0x0000022d

#define TEGRA264_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT	0x00000230

#define TEGRA264_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT	0x00000233

#define TEGRA264_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT	0x00000236

#define TEGRA264_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT	0x00000239

#define TEGRA264_ADMAIF_RX21_FIFO_CTRL_REG_DEFAULT	0x0000023c

#define TEGRA264_ADMAIF_RX22_FIFO_CTRL_REG_DEFAULT	0x0000023f

#define TEGRA264_ADMAIF_RX23_FIFO_CTRL_REG_DEFAULT	0x00000242

#define TEGRA264_ADMAIF_RX24_FIFO_CTRL_REG_DEFAULT	0x00000245

#define TEGRA264_ADMAIF_RX25_FIFO_CTRL_REG_DEFAULT	0x00000248

#define TEGRA264_ADMAIF_RX26_FIFO_CTRL_REG_DEFAULT	0x0000024b

#define TEGRA264_ADMAIF_RX27_FIFO_CTRL_REG_DEFAULT	0x0000024e

#define TEGRA264_ADMAIF_RX28_FIFO_CTRL_REG_DEFAULT	0x00000251

#define TEGRA264_ADMAIF_RX29_FIFO_CTRL_REG_DEFAULT	0x00000254

#define TEGRA264_ADMAIF_RX30_FIFO_CTRL_REG_DEFAULT	0x00000257

#define TEGRA264_ADMAIF_RX31_FIFO_CTRL_REG_DEFAULT	0x0000025a

#define TEGRA264_ADMAIF_RX32_FIFO_CTRL_REG_DEFAULT	0x0000025d

#define TEGRA264_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT	0x01800200

#define TEGRA264_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT	0x01800203

#define TEGRA264_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT	0x01800206

#define TEGRA264_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT	0x01800209

#define TEGRA264_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT	0x0180020c

#define TEGRA264_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT	0x0180020f

#define TEGRA264_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT	0x01800212

#define TEGRA264_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT	0x01800215

#define TEGRA264_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT	0x01800218

#define TEGRA264_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT	0x0180021b

#define TEGRA264_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT	0x0180021e

#define TEGRA264_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT	0x01800221

#define TEGRA264_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT	0x01800224

#define TEGRA264_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT	0x01800227

#define TEGRA264_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT	0x0180022a

#define TEGRA264_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT	0x0180022d

#define TEGRA264_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT	0x01800230

#define TEGRA264_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT	0x01800233

#define TEGRA264_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT	0x01800236

#define TEGRA264_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT	0x01800239

#define TEGRA264_ADMAIF_TX21_FIFO_CTRL_REG_DEFAULT	0x0180023c

#define TEGRA264_ADMAIF_TX22_FIFO_CTRL_REG_DEFAULT	0x0180023f

#define TEGRA264_ADMAIF_TX23_FIFO_CTRL_REG_DEFAULT	0x01800242

#define TEGRA264_ADMAIF_TX24_FIFO_CTRL_REG_DEFAULT	0x01800245

#define TEGRA264_ADMAIF_TX25_FIFO_CTRL_REG_DEFAULT	0x01800248

#define TEGRA264_ADMAIF_TX26_FIFO_CTRL_REG_DEFAULT	0x0180024b

#define TEGRA264_ADMAIF_TX27_FIFO_CTRL_REG_DEFAULT	0x0180024e

#define TEGRA264_ADMAIF_TX28_FIFO_CTRL_REG_DEFAULT	0x01800251

#define TEGRA264_ADMAIF_TX29_FIFO_CTRL_REG_DEFAULT	0x01800254

#define TEGRA264_ADMAIF_TX30_FIFO_CTRL_REG_DEFAULT	0x01800257

#define TEGRA264_ADMAIF_TX31_FIFO_CTRL_REG_DEFAULT	0x0180025a

#define TEGRA264_ADMAIF_TX32_FIFO_CTRL_REG_DEFAULT	0x0180025d



enum {

	DATA_8BIT,
@@ -148,6 +225,7 @@ struct tegra_admaif_soc_data { 
	unsigned int tx_base;

	unsigned int rx_base;

	unsigned int num_ch;

	unsigned int max_stream_ch;

};



struct tegra_admaif {