Commit 767ae437 authored by Rik van Riel's avatar Rik van Riel Committed by Ingo Molnar
Browse files

x86/mm: Add INVLPGB feature and Kconfig entry 



In addition, the CPU advertises the maximum number of pages that can be
shot down with one INVLPGB instruction in CPUID. Save that information
for later use.

  [ bp: use cpu_has(), typos, massage. ]

Signed-off-by: default avatarRik van Riel <riel@surriel.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20250226030129.530345-3-riel@surriel.com
parent 4a02ed8e

arch/x86/Kconfig.cpu

+4 −0
Original line number Diff line number Diff line
@@ -334,6 +334,10 @@ menuconfig PROCESSOR_SELECT 
	  This lets you choose what x86 vendor support code your kernel

	  will include.



config BROADCAST_TLB_FLUSH

	def_bool y

	depends on CPU_SUP_AMD && 64BIT



config CPU_SUP_INTEL

	default y

	bool "Support Intel processors" if PROCESSOR_SELECT

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -338,6 +338,7 @@ 
#define X86_FEATURE_CLZERO		(13*32+ 0) /* "clzero" CLZERO instruction */

#define X86_FEATURE_IRPERF		(13*32+ 1) /* "irperf" Instructions Retired Count */

#define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */

#define X86_FEATURE_INVLPGB		(13*32+ 3) /* INVLPGB and TLBSYNC instructions supported */

#define X86_FEATURE_RDPRU		(13*32+ 4) /* "rdpru" Read processor register at user level */

#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */

#define X86_FEATURE_AMD_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier */

arch/x86/include/asm/disabled-features.h

+7 −1
Original line number Diff line number Diff line
@@ -129,6 +129,12 @@ 
#define DISABLE_SEV_SNP		(1 << (X86_FEATURE_SEV_SNP & 31))

#endif



#ifdef CONFIG_BROADCAST_TLB_FLUSH

#define DISABLE_INVLPGB		0

#else

#define DISABLE_INVLPGB		(1 << (X86_FEATURE_INVLPGB & 31))

#endif



/*

 * Make sure to add features to the correct mask

 */
@@ -146,7 +152,7 @@ 
#define DISABLED_MASK11	(DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \

			 DISABLE_CALL_DEPTH_TRACKING|DISABLE_USER_SHSTK)

#define DISABLED_MASK12	(DISABLE_FRED|DISABLE_LAM)

#define DISABLED_MASK13	0

#define DISABLED_MASK13	(DISABLE_INVLPGB)

#define DISABLED_MASK14	0

#define DISABLED_MASK15	0

#define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \

arch/x86/include/asm/tlbflush.h

+3 −0
Original line number Diff line number Diff line
@@ -183,6 +183,9 @@ static inline void cr4_init_shadow(void) 
extern unsigned long mmu_cr4_features;

extern u32 *trampoline_cr4_features;



/* How many pages can be invalidated with one INVLPGB. */

extern u16 invlpgb_count_max;



extern void initialize_tlbstate_and_flush(void);



/*

arch/x86/kernel/cpu/amd.c

+6 −0
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 


#include "cpu.h"



u16 invlpgb_count_max __ro_after_init;



static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)

{

	u32 gprs[8] = { 0 };
@@ -1139,6 +1141,10 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 
		tlb_lli_2m = eax & mask;



	tlb_lli_4m = tlb_lli_2m >> 1;



	/* Max number of pages INVLPGB can invalidate in one shot */

	if (cpu_has(c, X86_FEATURE_INVLPGB))

		invlpgb_count_max = (cpuid_edx(0x80000008) & 0xffff) + 1;

}



static const struct cpu_dev amd_cpu_dev = {