Commit 76830926 authored by Angelo Dureghello's avatar Angelo Dureghello Committed by Jonathan Cameron
Browse files

dt-bindings: iio: dac: ad3552r: add iio backend support 



There is a version of AXI DAC IP block (for FPGAs) that provides
a physical QSPI bus for AD3552R and similar chips, so supporting
spi-controller functionalities.

For this case, the binding is modified to include some additional
properties.

Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarAngelo Dureghello <adureghello@baylibre.com>
Reviewed-by: default avatarDavid Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-1-f6960b4f9719@kernel-space.org


Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent f928099e

Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml

+7 −0
Original line number Diff line number Diff line
@@ -60,6 +60,12 @@ properties: 
    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [0, 1, 2, 3]



  io-backends:

    description: The iio backend reference.

      Device can be optionally connected to the "axi-ad3552r IP" fpga-based

      QSPI + DDR (Double Data Rate) controller to reach high speed transfers.

    maxItems: 1



  '#address-cells':

    const: 1
@@ -128,6 +134,7 @@ patternProperties: 
          - custom-output-range-config



allOf:

  - $ref: /schemas/spi/spi-peripheral-props.yaml#

  - if:

      properties:

        compatible: