Commit 76889bba authored by Jason Gunthorpe's avatar Jason Gunthorpe
Browse files

Merge branch 'nesting_reserved_regions' into iommufd.git for-next 

Nicolin Chen says:

=========
IOMMU_RESV_SW_MSI is a unique region defined by an IOMMU driver. Though it
is eventually used by a device for address translation to an MSI location
(including nested cases), practically it is a universal region across all
domains allocated for the IOMMU that defines it.

Currently IOMMUFD core fetches and reserves the region during an attach to
an hwpt_paging. It works with a hwpt_paging-only case, but might not work
with a nested case where a device could directly attach to a hwpt_nested,
bypassing the hwpt_paging attachment.

Move the enforcement forward, to the hwpt_paging allocation function. Then
clean up all the SW_MSI related things in the attach/replace routine.
=========

Based on v6.11-rc5 for dependencies.

* nesting_reserved_regions: (562 commits)
  iommufd/device: Enforce reserved IOVA also when attached to hwpt_nested
  Linux 6.11-rc5
  ...
parents 79ea4a49 b2f44814

Documentation/ABI/testing/sysfs-devices-system-cpu

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@@ -562,7 +562,8 @@ Description: Control Symmetric Multi Threading (SMT) 
			 ================ =========================================



			 If control status is "forceoff" or "notsupported" writes

			 are rejected.

			 are rejected. Note that enabling SMT on PowerPC skips

			 offline cores.



What:		/sys/devices/system/cpu/cpuX/power/energy_perf_bias

Date:		March 2019

Documentation/admin-guide/device-mapper/dm-crypt.rst

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@@ -162,6 +162,7 @@ iv_large_sectors 




Module parameters::



   max_read_size

   max_write_size

      Maximum size of read or write requests. When a request larger than this size

Documentation/arch/riscv/hwprobe.rst

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@@ -239,25 +239,33 @@ The following keys are defined: 
       ratified in commit 98918c844281 ("Merge pull request #1217 from

       riscv/zawrs") of riscv-isa-manual.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to

     :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was

     mistakenly classified as a bitmask rather than a value.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned

    accesses is unknown.

* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing

  the performance of misaligned scalar native word accesses on the selected set

  of processors.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are

    emulated via software, either in or below the kernel.  These accesses are

    always extremely slow.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of

    misaligned scalar accesses is unknown.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower

    than equivalent byte accesses.  Misaligned accesses may be supported

    directly in hardware, or trapped and emulated by software.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar

    accesses are emulated via software, either in or below the kernel.  These

    accesses are always extremely slow.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster

    than equivalent byte accesses.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native

    word sized accesses are slower than the equivalent quantity of byte

    accesses. Misaligned accesses may be supported directly in hardware, or

    trapped and emulated by software.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are

    not supported at all and will generate a misaligned address fault.

  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native

    word sized accesses are faster than the equivalent quantity of byte

    accesses.



  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar

    accesses are not supported at all and will generate a misaligned address

    fault.



* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which

  represents the size of the Zicboz block in bytes.

Documentation/core-api/workqueue.rst

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@@ -260,7 +260,7 @@ Some users depend on strict execution ordering where only one work item 
is in flight at any given time and the work items are processed in

queueing order. While the combination of ``@max_active`` of 1 and

``WQ_UNBOUND`` used to achieve this behavior, this is no longer the

case. Use ``alloc_ordered_queue()`` instead.

case. Use alloc_ordered_workqueue() instead.





Example Execution Scenarios

Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Qualcomm Display Clock & Reset Controller on SM6350



maintainers:

  - Konrad Dybcio <konrad.dybcio@somainline.org>

  - Konrad Dybcio <konradybcio@kernel.org>



description: |

  Qualcomm display clock control module provides the clocks, resets and power