Commit 77218e83 authored by Haris Okanovic's avatar Haris Okanovic Committed by Jarkko Sakkinen
Browse files

tpm_tis: fix stall after iowrite*()s 



ioread8() operations to TPM MMIO addresses can stall the CPU when
immediately following a sequence of iowrite*()'s to the same region.

For example, cyclitest measures ~400us latency spikes when a non-RT
usermode application communicates with an SPI-based TPM chip (Intel Atom
E3940 system, PREEMPT_RT kernel). The spikes are caused by a
stalling ioread8() operation following a sequence of 30+ iowrite8()s to
the same address. I believe this happens because the write sequence is
buffered (in CPU or somewhere along the bus), and gets flushed on the
first LOAD instruction (ioread*()) that follows.

The enclosed change appears to fix this issue: read the TPM chip's
access register (status code) after every iowrite*() operation to
amortize the cost of flushing data to chip across multiple instructions.

Signed-off-by: default avatarHaris Okanovic <haris.okanovic@ni.com>
Link: https://lore.kernel.org/r/20230323153436.B2SATnZV@linutronix.de


Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Tested-by: default avatarJarkko Sakkinen <jarkko@kernel.org>
Reviewed-by: default avatarJarkko Sakkinen <jarkko@kernel.org>
Signed-off-by: default avatarJarkko Sakkinen <jarkko@kernel.org>
parent 7b69ef62

drivers/char/tpm/tpm_tis.c

+41 −2
Original line number Diff line number Diff line
@@ -50,6 +50,45 @@ static inline struct tpm_tis_tcg_phy *to_tpm_tis_tcg_phy(struct tpm_tis_data *da 
	return container_of(data, struct tpm_tis_tcg_phy, priv);

}



#ifdef CONFIG_PREEMPT_RT

/*

 * Flush previous write operations with a dummy read operation to the

 * TPM MMIO base address.

 */

static inline void tpm_tis_flush(void __iomem *iobase)

{

	ioread8(iobase + TPM_ACCESS(0));

}

#else

#define tpm_tis_flush(iobase) do { } while (0)

#endif



/*

 * Write a byte word to the TPM MMIO address, and flush the write queue.

 * The flush ensures that the data is sent immediately over the bus and not

 * aggregated with further requests and transferred later in a batch. The large

 * write requests can lead to unwanted latency spikes by blocking the CPU until

 * the complete batch has been transferred.

 */

static inline void tpm_tis_iowrite8(u8 b, void __iomem *iobase, u32 addr)

{

	iowrite8(b, iobase + addr);

	tpm_tis_flush(iobase);

}



/*

 * Write a 32-bit word to the TPM MMIO address, and flush the write queue.

 * The flush ensures that the data is sent immediately over the bus and not

 * aggregated with further requests and transferred later in a batch. The large

 * write requests can lead to unwanted latency spikes by blocking the CPU until

 * the complete batch has been transferred.

 */

static inline void tpm_tis_iowrite32(u32 b, void __iomem *iobase, u32 addr)

{

	iowrite32(b, iobase + addr);

	tpm_tis_flush(iobase);

}



static int interrupts = -1;

module_param(interrupts, int, 0444);

MODULE_PARM_DESC(interrupts, "Enable interrupts");
@@ -186,12 +225,12 @@ static int tpm_tcg_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len, 
	switch (io_mode) {

	case TPM_TIS_PHYS_8:

		while (len--)

			iowrite8(*value++, phy->iobase + addr);

			tpm_tis_iowrite8(*value++, phy->iobase, addr);

		break;

	case TPM_TIS_PHYS_16:

		return -EINVAL;

	case TPM_TIS_PHYS_32:

		iowrite32(le32_to_cpu(*((__le32 *)value)), phy->iobase + addr);

		tpm_tis_iowrite32(le32_to_cpu(*((__le32 *)value)), phy->iobase, addr);

		break;

	}