Unverified Commit 77289a8a authored by Miquel Raynal's avatar Miquel Raynal Committed by Mark Brown
Browse files

spi: dt-bindings: cdns,qspi-nor: Be more descriptive regarding what this controller is 



Despite being very common in commit logs, SPI NOR controllers simply do
not exist. At least, they are not as specific as the name implies. There
are SPI memory controllers which are indeed "specialized" and optimized
for handling "memories", but most of them are just generic and accept
almost any kind of opcode, address, dummy and data cycles, making them
as suitable for NANDs than NORs.

Furthermore, this controller supports any kind of bus, from single to
octal NAND, so make it clear.

Also add a comment to mention that the initial compatible naming is too
specific (but obviously kept for backward compatibility reasons).

Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250319094651.1290509-2-miquel.raynal@bootlin.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 48303ef3

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

+4 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Cadence Quad SPI controller

title: Cadence Quad/Octal SPI controller



maintainers:

  - Vaishnav Achath <vaishnav.a@ti.com>
@@ -76,6 +76,9 @@ properties: 
              - ti,am654-ospi

              - ti,k2g-qspi

              - xlnx,versal-ospi-1.0

          # The compatible is qspi-nor for historical reasons but such

          # controllers are meant to be used with flashes of all kinds,

          # ie. also NAND flashes, not only NOR flashes.

          - const: cdns,qspi-nor

      - const: cdns,qspi-nor