Commit 773d1bca authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
Browse files

drm/amd/display: remove independent lock as we have no use case today 



Signed-off-by: default avatarTony Cheng <tony.cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d98e5cc2

drivers/gpu/drm/amd/display/dc/core/dc.c

+0 −8
Original line number Diff line number Diff line
@@ -1178,7 +1178,6 @@ void dc_update_surfaces_for_stream(struct dc *dc, 


	enum surface_update_type update_type;

	const struct dc_stream_status *stream_status;

	unsigned int lock_mask = 0;



	stream_status = dc_stream_get_status(dc_stream);

	ASSERT(stream_status);
@@ -1332,15 +1331,9 @@ void dc_update_surfaces_for_stream(struct dc *dc, 
			}



			if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {

				lock_mask = PIPE_LOCK_CONTROL_GRAPHICS |

						PIPE_LOCK_CONTROL_SCL |

						PIPE_LOCK_CONTROL_BLENDER |

						PIPE_LOCK_CONTROL_MODE;



				core_dc->hwss.pipe_control_lock(

						core_dc,

						pipe_ctx,

						lock_mask,

						true);

			}
@@ -1382,7 +1375,6 @@ void dc_update_surfaces_for_stream(struct dc *dc, 
					core_dc->hwss.pipe_control_lock(

							core_dc,

							pipe_ctx,

							lock_mask,

							false);

				}

				break;

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c

+5 −14
Original line number Diff line number Diff line
@@ -46,7 +46,6 @@ void dce_enable_fe_clock(struct dce_hwseq *hws, 


void dce_pipe_control_lock(struct core_dc *dc,

		struct pipe_ctx *pipe,

		enum pipe_lock_control control_mask,

		bool lock)

{

	uint32_t lock_val = lock ? 1 : 0;
@@ -59,19 +58,11 @@ void dce_pipe_control_lock(struct core_dc *dc, 
			BLND_BLND_V_UPDATE_LOCK, &blnd,

			BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);



	if (control_mask & PIPE_LOCK_CONTROL_GRAPHICS)

	dcp_grph = lock_val;



	if (control_mask & PIPE_LOCK_CONTROL_SCL)

	scl = lock_val;



	if (control_mask & PIPE_LOCK_CONTROL_BLENDER)

	blnd = lock_val;



	if (control_mask & PIPE_LOCK_CONTROL_MODE)

	update_lock_mode = lock_val;





	REG_SET_2(BLND_V_UPDATE_LOCK[pipe->pipe_idx], val,

			BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,

			BLND_SCL_V_UPDATE_LOCK, scl);
@@ -82,7 +73,7 @@ void dce_pipe_control_lock(struct core_dc *dc, 
				BLND_V_UPDATE_LOCK_MODE, update_lock_mode);



	if (hws->wa.blnd_crtc_trigger) {

		if (!lock && (control_mask & PIPE_LOCK_CONTROL_BLENDER)) {

		if (!lock) {

			uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->pipe_idx]);

			REG_WRITE(CRTC_H_BLANK_START_END[pipe->pipe_idx], value);

		}

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

+0 −1
Original line number Diff line number Diff line
@@ -224,7 +224,6 @@ void dce_enable_fe_clock(struct dce_hwseq *hwss, 


void dce_pipe_control_lock(struct core_dc *dc,

		struct pipe_ctx *pipe,

		enum pipe_lock_control control_mask,

		bool lock);



void dce_set_blender_mode(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

+0 −8
Original line number Diff line number Diff line
@@ -34,13 +34,6 @@ enum pipe_gating_control { 
	PIPE_GATING_CONTROL_INIT

};



enum pipe_lock_control {

	PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,

	PIPE_LOCK_CONTROL_BLENDER = 1 << 1,

	PIPE_LOCK_CONTROL_SCL = 1 << 2,

	PIPE_LOCK_CONTROL_MODE = 1 << 3,

};



struct dce_hwseq_wa {

	bool blnd_crtc_trigger;

};
@@ -128,7 +121,6 @@ struct hw_sequencer_funcs { 
	void (*pipe_control_lock)(

				struct core_dc *dc,

				struct pipe_ctx *pipe,

				enum pipe_lock_control control_mask,

				bool lock);



	void (*set_displaymarks)(