Commit 77633c77 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'bitmap-for-6.18' of https://github.com/norov/linux 

Pull bitmap updates from Yury Norov:

 - FIELD_PREP_WM16() consolidation (Nicolas)

 - bitmaps for Rust (Burak)

 - __fls() fix for arc (Kees)

* tag 'bitmap-for-6.18' of https://github.com/norov/linux: (25 commits)
  rust: add dynamic ID pool abstraction for bitmap
  rust: add find_bit_benchmark_rust module.
  rust: add bitmap API.
  rust: add bindings for bitops.h
  rust: add bindings for bitmap.h
  phy: rockchip-pcie: switch to FIELD_PREP_WM16 macro
  clk: sp7021: switch to FIELD_PREP_WM16 macro
  PCI: dw-rockchip: Switch to FIELD_PREP_WM16 macro
  PCI: rockchip: Switch to FIELD_PREP_WM16* macros
  net: stmmac: dwmac-rk: switch to FIELD_PREP_WM16 macro
  ASoC: rockchip: i2s-tdm: switch to FIELD_PREP_WM16_CONST macro
  drm/rockchip: dw_hdmi: switch to FIELD_PREP_WM16* macros
  phy: rockchip-usb: switch to FIELD_PREP_WM16 macro
  drm/rockchip: inno-hdmi: switch to FIELD_PREP_WM16 macro
  drm/rockchip: dw_hdmi_qp: switch to FIELD_PREP_WM16 macro
  phy: rockchip-samsung-dcphy: switch to FIELD_PREP_WM16 macro
  drm/rockchip: vop2: switch to FIELD_PREP_WM16 macro
  drm/rockchip: dsi: switch to FIELD_PREP_WM16* macros
  phy: rockchip-emmc: switch to FIELD_PREP_WM16 macro
  drm/rockchip: lvds: switch to FIELD_PREP_WM16 macro
  ...
parents d7a018eb 2cdae413

MAINTAINERS

+16 −0
Original line number Diff line number Diff line
@@ -4298,6 +4298,7 @@ F: include/linux/bits.h 
F:	include/linux/cpumask.h

F:	include/linux/cpumask_types.h

F:	include/linux/find.h

F:	include/linux/hw_bitfield.h

F:	include/linux/nodemask.h

F:	include/linux/nodemask_types.h

F:	include/uapi/linux/bits.h
@@ -4321,8 +4322,18 @@ F: tools/lib/find_bit.c 
BITMAP API BINDINGS [RUST]

M:	Yury Norov <yury.norov@gmail.com>

S:	Maintained

F:	rust/helpers/bitmap.c

F:	rust/helpers/cpumask.c









BITMAP API [RUST]









M:	Alice Ryhl <aliceryhl@google.com>









M:	Burak Emir <bqe@google.com>









R:	Yury Norov <yury.norov@gmail.com>









S:	Maintained









F:	lib/find_bit_benchmark_rust.rs









F:	rust/kernel/bitmap.rs









F:	rust/kernel/id_pool.rs

















BITOPS API









M:	Yury Norov <yury.norov@gmail.com>









R:	Rasmus Villemoes <linux@rasmusvillemoes.dk>








@@ -4337,6 +4348,11 @@ F:	include/linux/bitops.h







F:	lib/test_bitops.c









F:	tools/*/bitops*

















BITOPS API BINDINGS [RUST]









M:	Yury Norov <yury.norov@gmail.com>









S:	Maintained









F:	rust/helpers/bitops.c

















BLINKM RGB LED DRIVER









M:	Jan-Simon Moeller <jansimon.moeller@gmx.de>









S:	Maintained
































arch/arc/include/asm/bitops.h



+2
−0






























Original line number
Diff line number
Diff line







@@ -133,6 +133,8 @@ static inline __attribute__ ((const)) int fls(unsigned int x)







 */









static inline __attribute__ ((const)) unsigned long __fls(unsigned long x)









{









	if (__builtin_constant_p(x))









		return x ? BITS_PER_LONG - 1 - __builtin_clzl(x) : 0;









	/* FLS insn has exactly same semantics as the API */









	return	__builtin_arc_fls(x);









}
































drivers/clk/clk-sp7021.c



+8
−14






























Original line number
Diff line number
Diff line







@@ -7,6 +7,7 @@







#include <linux/clk-provider.h>









#include <linux/of.h>









#include <linux/bitfield.h>









#include <linux/hw_bitfield.h>









#include <linux/slab.h>









#include <linux/io.h>









#include <linux/err.h>








@@ -38,13 +39,6 @@ enum {







#define MASK_DIVN	GENMASK(7, 0)









#define MASK_DIVM	GENMASK(14, 8)



















/* HIWORD_MASK FIELD_PREP */









#define HWM_FIELD_PREP(mask, value)		\









({						\









	u64 _m = mask;				\









	(_m << 16) | FIELD_PREP(_m, value);	\









})



















struct sp_pll {









	struct clk_hw hw;









	void __iomem *reg;








@@ -313,15 +307,15 @@ static int plltv_set_rate(struct sp_pll *clk)







	u32 r0, r1, r2;



















	r0  = BIT(clk->bp_bit + 16);









	r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]);









	r0 |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]);









	r0 |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]);









	r0 |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]);









	r0 |= FIELD_PREP_WM16(MASK_SEL_FRA, clk->p[SEL_FRA]);









	r0 |= FIELD_PREP_WM16(MASK_SDM_MOD, clk->p[SDM_MOD]);









	r0 |= FIELD_PREP_WM16(MASK_PH_SEL, clk->p[PH_SEL]);









	r0 |= FIELD_PREP_WM16(MASK_NFRA, clk->p[NFRA]);



















	r1  = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]);









	r1  = FIELD_PREP_WM16(MASK_DIVR, clk->p[DIVR]);



















	r2  = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1);









	r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1);









	r2  = FIELD_PREP_WM16(MASK_DIVN, clk->p[DIVN] - 1);









	r2 |= FIELD_PREP_WM16(MASK_DIVM, clk->p[DIVM] - 1);



















	spin_lock_irqsave(&clk->lock, flags);









	writel(r0, clk->reg);
































drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c



+68
−74






























Original line number
Diff line number
Diff line







@@ -7,6 +7,7 @@







 */



















#include <linux/clk.h>









#include <linux/hw_bitfield.h>









#include <linux/iopoll.h>









#include <linux/math64.h>









#include <linux/mfd/syscon.h>








@@ -148,7 +149,7 @@







#define DW_MIPI_NEEDS_GRF_CLK		BIT(1)



















#define PX30_GRF_PD_VO_CON1		0x0438









#define PX30_DSI_FORCETXSTOPMODE	(0xf << 7)









#define PX30_DSI_FORCETXSTOPMODE	(0xfUL << 7)









#define PX30_DSI_FORCERXMODE		BIT(6)









#define PX30_DSI_TURNDISABLE		BIT(5)









#define PX30_DSI_LCDC_SEL		BIT(0)








@@ -167,16 +168,16 @@







#define RK3399_DSI1_LCDC_SEL		BIT(4)



















#define RK3399_GRF_SOC_CON22		0x6258









#define RK3399_DSI0_TURNREQUEST		(0xf << 12)









#define RK3399_DSI0_TURNDISABLE		(0xf << 8)









#define RK3399_DSI0_FORCETXSTOPMODE	(0xf << 4)









#define RK3399_DSI0_FORCERXMODE		(0xf << 0)









#define RK3399_DSI0_TURNREQUEST		(0xfUL << 12)









#define RK3399_DSI0_TURNDISABLE		(0xfUL << 8)









#define RK3399_DSI0_FORCETXSTOPMODE	(0xfUL << 4)









#define RK3399_DSI0_FORCERXMODE		(0xfUL << 0)



















#define RK3399_GRF_SOC_CON23		0x625c









#define RK3399_DSI1_TURNDISABLE		(0xf << 12)









#define RK3399_DSI1_FORCETXSTOPMODE	(0xf << 8)









#define RK3399_DSI1_FORCERXMODE		(0xf << 4)









#define RK3399_DSI1_ENABLE		(0xf << 0)









#define RK3399_DSI1_TURNDISABLE		(0xfUL << 12)









#define RK3399_DSI1_FORCETXSTOPMODE	(0xfUL << 8)









#define RK3399_DSI1_FORCERXMODE		(0xfUL << 4)









#define RK3399_DSI1_ENABLE		(0xfUL << 0)



















#define RK3399_GRF_SOC_CON24		0x6260









#define RK3399_TXRX_MASTERSLAVEZ	BIT(7)








@@ -186,8 +187,8 @@







#define RK3399_TXRX_TURNREQUEST		GENMASK(3, 0)



















#define RK3568_GRF_VO_CON2		0x0368









#define RK3568_DSI0_SKEWCALHS		(0x1f << 11)









#define RK3568_DSI0_FORCETXSTOPMODE	(0xf << 4)









#define RK3568_DSI0_SKEWCALHS		(0x1fUL << 11)









#define RK3568_DSI0_FORCETXSTOPMODE	(0xfUL << 4)









#define RK3568_DSI0_TURNDISABLE		BIT(2)









#define RK3568_DSI0_FORCERXMODE		BIT(0)


















@@ -197,18 +198,16 @@







 * come from. Name GRF_VO_CON3 is assumed.









 */









#define RK3568_GRF_VO_CON3		0x36c









#define RK3568_DSI1_SKEWCALHS		(0x1f << 11)









#define RK3568_DSI1_FORCETXSTOPMODE	(0xf << 4)









#define RK3568_DSI1_SKEWCALHS		(0x1fUL << 11)









#define RK3568_DSI1_FORCETXSTOPMODE	(0xfUL << 4)









#define RK3568_DSI1_TURNDISABLE		BIT(2)









#define RK3568_DSI1_FORCERXMODE		BIT(0)



















#define RV1126_GRF_DSIPHY_CON		0x10220









#define RV1126_DSI_FORCETXSTOPMODE	(0xf << 4)









#define RV1126_DSI_FORCETXSTOPMODE	(0xfUL << 4)









#define RV1126_DSI_TURNDISABLE		BIT(2)









#define RV1126_DSI_FORCERXMODE		BIT(0)



















#define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)



















enum {









	DW_DSI_USAGE_IDLE,









	DW_DSI_USAGE_DSI,








@@ -1484,14 +1483,13 @@ static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {







	{









		.reg = 0xff450000,









		.lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,









		.lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),









		.lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,









					    PX30_DSI_LCDC_SEL),









		.lcdsel_big = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 0),









		.lcdsel_lit = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 1),



















		.lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,









		.lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |









		.lanecfg1 = FIELD_PREP_WM16_CONST((PX30_DSI_TURNDISABLE |









						PX30_DSI_FORCERXMODE |









					     PX30_DSI_FORCETXSTOPMODE),









						PX30_DSI_FORCETXSTOPMODE), 0),



















		.max_data_lanes = 4,









	},








@@ -1502,9 +1500,9 @@ static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = {







	{









		.reg = 0x10110000,









		.lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0,









		.lanecfg1 = HIWORD_UPDATE(0, RK3128_DSI_TURNDISABLE |









		.lanecfg1 = FIELD_PREP_WM16_CONST((RK3128_DSI_TURNDISABLE |









						RK3128_DSI_FORCERXMODE |









					     RK3128_DSI_FORCETXSTOPMODE),









						RK3128_DSI_FORCETXSTOPMODE), 0),









		.max_data_lanes = 4,









	},









	{ /* sentinel */ }








@@ -1514,16 +1512,16 @@ static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {







	{









		.reg = 0xff960000,









		.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,









		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),









		.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),









		.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 0),









		.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1),



















		.max_data_lanes = 4,









	},









	{









		.reg = 0xff964000,









		.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,









		.lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),









		.lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),









		.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 0),









		.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1),



















		.max_data_lanes = 4,









	},








@@ -1539,13 +1537,13 @@ static int rk3399_dphy_tx1rx1_init(struct phy *phy)







	 * Assume ISP0 is supplied by the RX0 dphy.









	 */









	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,









		     HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0));









		     FIELD_PREP_WM16(RK3399_TXRX_SRC_SEL_ISP0, 0));









	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,









		     HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));









		     FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));









	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,









		     HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR));









		     FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 0));









	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,









		     HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));









		     FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));



















	return 0;









}








@@ -1559,21 +1557,20 @@ static int rk3399_dphy_tx1rx1_power_on(struct phy *phy)







	usleep_range(100, 150);



















	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,









		     HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ));









		     FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0));









	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,









		     HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR));









		     FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 1));



















	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,









		     HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE));









		     FIELD_PREP_WM16(RK3399_DSI1_FORCERXMODE, 0));









	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,









		     HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE));









		     FIELD_PREP_WM16(RK3399_DSI1_FORCETXSTOPMODE, 0));



















	/* Disable lane turn around, which is ignored in receive mode */









	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,









		     HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST));









		     FIELD_PREP_WM16(RK3399_TXRX_TURNREQUEST, 0));









	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,









		     HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE,









				   RK3399_DSI1_TURNDISABLE));









		     FIELD_PREP_WM16(RK3399_DSI1_TURNDISABLE, 0xf));









	usleep_range(100, 150);



















	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);








@@ -1581,8 +1578,8 @@ static int rk3399_dphy_tx1rx1_power_on(struct phy *phy)

















	/* Enable dphy lanes */









	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,









		     HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),









				   RK3399_DSI1_ENABLE));









		     FIELD_PREP_WM16(RK3399_DSI1_ENABLE,









				  GENMASK(dsi->dphy_config.lanes - 1, 0)));



















	usleep_range(100, 150);


















@@ -1594,7 +1591,7 @@ static int rk3399_dphy_tx1rx1_power_off(struct phy *phy)







	struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);



















	regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,









		     HIWORD_UPDATE(0, RK3399_DSI1_ENABLE));









		     FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0));



















	return 0;









}








@@ -1603,15 +1600,14 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {







	{









		.reg = 0xff960000,









		.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,









		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),









		.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,









					    RK3399_DSI0_LCDC_SEL),









		.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 0),









		.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 1),



















		.lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,









		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |









		.lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI0_TURNREQUEST |









						RK3399_DSI0_TURNDISABLE |









						RK3399_DSI0_FORCETXSTOPMODE |









					     RK3399_DSI0_FORCERXMODE),









						RK3399_DSI0_FORCERXMODE), 0),



















		.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,









		.max_data_lanes = 4,








@@ -1619,25 +1615,23 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {







	{









		.reg = 0xff968000,









		.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,









		.lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),









		.lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,









					    RK3399_DSI1_LCDC_SEL),









		.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 0),









		.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 1),





























		.lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,









		.lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |









		.lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI1_TURNDISABLE |









						RK3399_DSI1_FORCETXSTOPMODE |









						RK3399_DSI1_FORCERXMODE |









					     RK3399_DSI1_ENABLE),









						RK3399_DSI1_ENABLE), 0),



















		.lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,









		.lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |









					  RK3399_TXRX_ENABLECLK,









					  RK3399_TXRX_MASTERSLAVEZ |









					  RK3399_TXRX_ENABLECLK |









					  RK3399_TXRX_BASEDIR),









		.lanecfg2 = (FIELD_PREP_WM16_CONST(RK3399_TXRX_MASTERSLAVEZ, 1) |









			     FIELD_PREP_WM16_CONST(RK3399_TXRX_ENABLECLK, 1) |









			     FIELD_PREP_WM16_CONST(RK3399_TXRX_BASEDIR, 0)),



















		.enable_grf_reg = RK3399_GRF_SOC_CON23,









		.enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),









		.enable = FIELD_PREP_WM16_CONST(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),



















		.flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,









		.max_data_lanes = 4,








@@ -1653,19 +1647,19 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {







	{









		.reg = 0xfe060000,









		.lanecfg1_grf_reg = RK3568_GRF_VO_CON2,









		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |









					  RK3568_DSI0_FORCETXSTOPMODE |









					  RK3568_DSI0_TURNDISABLE |









					  RK3568_DSI0_FORCERXMODE),









		.lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI0_SKEWCALHS, 0) |









			     FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCETXSTOPMODE, 0) |









			     FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) |









			     FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)),









		.max_data_lanes = 4,









	},









	{









		.reg = 0xfe070000,









		.lanecfg1_grf_reg = RK3568_GRF_VO_CON3,









		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |









					  RK3568_DSI1_FORCETXSTOPMODE |









					  RK3568_DSI1_TURNDISABLE |









					  RK3568_DSI1_FORCERXMODE),









		.lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI1_SKEWCALHS, 0) |









			     FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCETXSTOPMODE, 0) |









			     FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) |









			     FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)),









		.max_data_lanes = 4,









	},









	{ /* sentinel */ }








@@ -1675,9 +1669,9 @@ static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = {







	{









		.reg = 0xffb30000,









		.lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON,









		.lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE |









					     RV1126_DSI_FORCERXMODE |









					     RV1126_DSI_FORCETXSTOPMODE),









		.lanecfg1 = (FIELD_PREP_WM16_CONST(RV1126_DSI_TURNDISABLE, 0) |









			     FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) |









			     FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)),









		.max_data_lanes = 4,









	},









	{ /* sentinel */ }
































drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c



+36
−44






























Original line number
Diff line number
Diff line







@@ -4,6 +4,7 @@







 */



















#include <linux/clk.h>









#include <linux/hw_bitfield.h>









#include <linux/mfd/syscon.h>









#include <linux/module.h>









#include <linux/platform_device.h>








@@ -54,8 +55,6 @@







#define RK3568_HDMI_SDAIN_MSK		BIT(15)









#define RK3568_HDMI_SCLIN_MSK		BIT(14)



















#define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)



















/**









 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips









 * @lcdsel_grf_reg: grf register offset of lcdc select








@@ -355,17 +354,14 @@ static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)

















	dw_hdmi_phy_setup_hpd(dw_hdmi, data);



















	regmap_write(hdmi->regmap,









		RK3228_GRF_SOC_CON6,









		HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |









			      RK3228_HDMI_SCL_VSEL,









			      RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |









			      RK3228_HDMI_SCL_VSEL));



















	regmap_write(hdmi->regmap,









		RK3228_GRF_SOC_CON2,









		HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,









			      RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));









	regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON6,









		     FIELD_PREP_WM16(RK3228_HDMI_HPD_VSEL, 1) |









		     FIELD_PREP_WM16(RK3228_HDMI_SDA_VSEL, 1) |









		     FIELD_PREP_WM16(RK3228_HDMI_SCL_VSEL, 1));



















	regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON2,









		     FIELD_PREP_WM16(RK3228_HDMI_SDAIN_MSK, 1) |









		     FIELD_PREP_WM16(RK3328_HDMI_SCLIN_MSK, 1));









}



















static enum drm_connector_status








@@ -377,15 +373,13 @@ dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)







	status = dw_hdmi_phy_read_hpd(dw_hdmi, data);



















	if (status == connector_status_connected)









		regmap_write(hdmi->regmap,









			RK3328_GRF_SOC_CON4,









			HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,









				      RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));









		regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4,









			     FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 1) |









			     FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 1));









	else









		regmap_write(hdmi->regmap,









			RK3328_GRF_SOC_CON4,









			HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |









					 RK3328_HDMI_SCL_5V));









		regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4,









			     FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) |









			     FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0));









	return status;









}


















@@ -396,21 +390,21 @@ static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)







	dw_hdmi_phy_setup_hpd(dw_hdmi, data);



















	/* Enable and map pins to 3V grf-controlled io-voltage */









	regmap_write(hdmi->regmap,









		RK3328_GRF_SOC_CON4,









		HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |









				 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |









				 RK3328_HDMI_HPD_5V));









	regmap_write(hdmi->regmap,









		RK3328_GRF_SOC_CON3,









		HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |









				 RK3328_HDMI_HPD5V_GRF |









				 RK3328_HDMI_CEC5V_GRF));









	regmap_write(hdmi->regmap,









		RK3328_GRF_SOC_CON2,









		HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,









			      RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |









			      RK3328_HDMI_HPD_IOE));









	regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4,









		     FIELD_PREP_WM16(RK3328_HDMI_HPD_SARADC, 0) |









		     FIELD_PREP_WM16(RK3328_HDMI_CEC_5V, 0) |









		     FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) |









		     FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0) |









		     FIELD_PREP_WM16(RK3328_HDMI_HPD_5V, 0));









	regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON3,









		     FIELD_PREP_WM16(RK3328_HDMI_SDA5V_GRF, 0) |









		     FIELD_PREP_WM16(RK3328_HDMI_SCL5V_GRF, 0) |









		     FIELD_PREP_WM16(RK3328_HDMI_HPD5V_GRF, 0) |









		     FIELD_PREP_WM16(RK3328_HDMI_CEC5V_GRF, 0));









	regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON2,









		     FIELD_PREP_WM16(RK3328_HDMI_SDAIN_MSK, 1) |









		     FIELD_PREP_WM16(RK3328_HDMI_SCLIN_MSK, 1) |









		     FIELD_PREP_WM16(RK3328_HDMI_HPD_IOE, 0));



















	dw_hdmi_rk3328_read_hpd(dw_hdmi, data);









}








@@ -438,8 +432,8 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {

















static struct rockchip_hdmi_chip_data rk3288_chip_data = {









	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,









	.lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),









	.lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),









	.lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_HDMI_LCDC_SEL, 0),









	.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_HDMI_LCDC_SEL, 1),









	.max_tmds_clock = 340000,









};


















@@ -475,8 +469,8 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {

















static struct rockchip_hdmi_chip_data rk3399_chip_data = {









	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,









	.lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),









	.lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),









	.lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_HDMI_LCDC_SEL, 0),









	.lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_HDMI_LCDC_SEL, 1),









	.max_tmds_clock = 594000,









};


















@@ -589,10 +583,8 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,

















	if (hdmi->chip_data == &rk3568_chip_data) {









		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,









			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |









					   RK3568_HDMI_SCLIN_MSK,









					   RK3568_HDMI_SDAIN_MSK |









					   RK3568_HDMI_SCLIN_MSK));









			     FIELD_PREP_WM16(RK3568_HDMI_SDAIN_MSK, 1) |









			     FIELD_PREP_WM16(RK3568_HDMI_SCLIN_MSK, 1));









	}



















	drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);