Commit 779b68a5 authored by Akhil P Oommen's avatar Akhil P Oommen Committed by Rob Clark
Browse files

drm/msm/a6xx: Fix out of bound IO access in a6xx_get_gmu_registers 



REG_A6XX_GMU_AO_AHB_FENCE_CTRL register falls under GMU's register
range. So, use gmu_write() routines to write to this register.

Fixes: 1707add8 ("drm/msm/a6xx: Add a6xx gpu state")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarAkhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/688993/


Message-ID: <20251118-kaana-gpu-support-v4-1-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent 036b3531

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

+1 −1
Original line number Diff line number Diff line
@@ -1255,7 +1255,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu, 
		return;



	/* Set the fence to ALLOW mode so we can access the registers */

	gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);

	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);



	_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2],

		&a6xx_state->gmu_registers[3], false);