Commit 77acc6b5 authored by Samuel Holland's avatar Samuel Holland Committed by Andrew Morton
Browse files

riscv: add support for kernel-mode FPU 

This is motivated by the amdgpu DRM driver, which needs floating-point
code to support recent hardware.  That code is not performance-critical,
so only provide a minimal non-preemptible implementation for now.

Support is limited to riscv64 because riscv32 requires runtime (libgcc)
assistance to convert between doubles and 64-bit integers.

Link: https://lkml.kernel.org/r/20240329072441.591471-12-samuel.holland@sifive.com


Signed-off-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Borislav Petkov (AMD) <bp@alien8.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Huacai Chen <chenhuacai@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Masahiro Yamada <masahiroy@kernel.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nathan Chancellor <nathan@kernel.org>
Cc: Nicolas Schier <nicolas@fjasle.eu>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: WANG Xuerui <git@xen0n.name>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
parent b0b8a15b

arch/riscv/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ config RISCV 
	select ARCH_HAS_GCOV_PROFILE_ALL

	select ARCH_HAS_GIGANTIC_PAGE

	select ARCH_HAS_KCOV

	select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && FPU

	select ARCH_HAS_MEMBARRIER_CALLBACKS

	select ARCH_HAS_MEMBARRIER_SYNC_CORE

	select ARCH_HAS_MMIOWB

arch/riscv/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -84,6 +84,9 @@ KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64i 


KBUILD_AFLAGS += -march=$(riscv-march-y)



# For C code built with floating-point support, exclude V but keep F and D.

CC_FLAGS_FPU  := -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)([^v_]*)v?/\1\2/')



KBUILD_CFLAGS += -mno-save-restore

KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)

arch/riscv/include/asm/fpu.h

0 → 100644
+16 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2023 SiFive

 */



#ifndef _ASM_RISCV_FPU_H

#define _ASM_RISCV_FPU_H



#include <asm/switch_to.h>



#define kernel_fpu_available()	has_fpu()



void kernel_fpu_begin(void);

void kernel_fpu_end(void);



#endif /* ! _ASM_RISCV_FPU_H */

arch/riscv/kernel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ obj-$(CONFIG_RISCV_MISALIGNED) += unaligned_access_speed.o 
obj-$(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)	+= copy-unaligned.o



obj-$(CONFIG_FPU)		+= fpu.o

obj-$(CONFIG_FPU)		+= kernel_mode_fpu.o

obj-$(CONFIG_RISCV_ISA_V)	+= vector.o

obj-$(CONFIG_RISCV_ISA_V)	+= kernel_mode_vector.o

obj-$(CONFIG_SMP)		+= smpboot.o

arch/riscv/kernel/kernel_mode_fpu.c

0 → 100644
+28 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (C) 2023 SiFive

 */



#include <linux/export.h>

#include <linux/preempt.h>



#include <asm/csr.h>

#include <asm/fpu.h>

#include <asm/processor.h>

#include <asm/switch_to.h>



void kernel_fpu_begin(void)

{

	preempt_disable();

	fstate_save(current, task_pt_regs(current));

	csr_set(CSR_SSTATUS, SR_FS);

}

EXPORT_SYMBOL_GPL(kernel_fpu_begin);



void kernel_fpu_end(void)

{

	csr_clear(CSR_SSTATUS, SR_FS);

	fstate_restore(current, task_pt_regs(current));

	preempt_enable();

}

EXPORT_SYMBOL_GPL(kernel_fpu_end);