Commit 77e1f16b authored by Neil Armstrong's avatar Neil Armstrong Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8650: Flatten the USB nodes 



Transition the USB controllers found in the SM8650 SoC to the newly
introduced, flattened representation of the Qualcomm USB block.

The reg and interrupts properties from the usb child node are merged
with their counterpart in the outer node, remaining properties and child
nodes are simply moved.

Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250811-topic-sm8x50-usb-flatten-v2-2-0bbb3ac292e4@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 33450878

arch/arm64/boot/dts/qcom/sm8650-hdk.dts

+2 −4
Original line number Diff line number Diff line
@@ -1310,12 +1310,10 @@ &ufs_mem_phy { 
 */



&usb_1 {

	status = "okay";

};



&usb_1_dwc3 {

	dr_mode = "otg";

	usb-role-switch;



	status = "okay";

};



&usb_1_dwc3_hs {

arch/arm64/boot/dts/qcom/sm8650-mtp.dts

+2 −4
Original line number Diff line number Diff line
@@ -857,12 +857,10 @@ &ufs_mem_phy { 
 */



&usb_1 {

	status = "okay";

};



&usb_1_dwc3 {

	dr_mode = "otg";

	usb-role-switch;



	status = "okay";

};



&usb_1_dwc3_hs {

arch/arm64/boot/dts/qcom/sm8650-qrd.dts

+2 −4
Original line number Diff line number Diff line
@@ -1293,12 +1293,10 @@ &ufs_mem_phy { 
 */



&usb_1 {

	status = "okay";

};



&usb_1_dwc3 {

	dr_mode = "otg";

	usb-role-switch;



	status = "okay";

};



&usb_1_dwc3_hs {

arch/arm64/boot/dts/qcom/sm8650.dtsi

+40 −46
Original line number Diff line number Diff line
@@ -5651,16 +5651,18 @@ usb_dp_qmpphy_dp_in: endpoint { 
			};

		};



		usb_1: usb@a6f8800 {

			compatible = "qcom,sm8650-dwc3", "qcom,dwc3";

			reg = <0 0x0a6f8800 0 0x400>;

		usb_1: usb@a600000 {

			compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3";

			reg = <0 0x0a600000 0 0xfc100>;



			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,

			interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,

					      <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,

					      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,

					      <&pdc 14 IRQ_TYPE_EDGE_RISING>,

					      <&pdc 15 IRQ_TYPE_EDGE_RISING>,

					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "pwr_event",

			interrupt-names = "dwc_usb3",

					  "pwr_event",

					  "hs_phy_irq",

					  "dp_hs_phy_irq",

					  "dm_hs_phy_irq",
@@ -5685,6 +5687,11 @@ usb_1: usb@a6f8800 { 


			resets = <&gcc GCC_USB30_PRIM_BCR>;



			phys = <&usb_1_hsphy>,

			       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;

			phy-names = "usb2-phy",

				    "usb3-phy";



			interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
@@ -5692,27 +5699,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 
			interconnect-names = "usb-ddr",

					     "apps-usb";



			power-domains = <&gcc USB30_PRIM_GDSC>;

			required-opps = <&rpmhpd_opp_nom>;



			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			status = "disabled";



			usb_1_dwc3: usb@a600000 {

				compatible = "snps,dwc3";

				reg = <0 0x0a600000 0 0xcd00>;



				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;



			iommus = <&apps_smmu 0x40 0>;



				phys = <&usb_1_hsphy>,

				       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;

				phy-names = "usb2-phy",

					    "usb3-phy";

			power-domains = <&gcc USB30_PRIM_GDSC>;

			required-opps = <&rpmhpd_opp_nom>;



			snps,hird-threshold = /bits/ 8 <0x0>;

			snps,usb2-gadget-lpm-disable;
@@ -5728,6 +5718,11 @@ usb_1_dwc3: usb@a600000 { 


			dma-coherent;



			#address-cells = <1>;

			#size-cells = <0>;



			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;
@@ -5748,7 +5743,6 @@ usb_1_dwc3_ss: endpoint { 
				};

			};

		};

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sm8650-pdc", "qcom,pdc";