Commit 781c336a authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/mpllb: move mpllb state check to intel_snps_phy.c 



Keep the mpllb implementation details together in intel_snps_phy.c. Also
declutter intel_display.c.

v2: intel_mpllb_verify_state -> void intel_mpllb_state_verify (Ville)

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e7340bb0e399aeb2676c4820461187eeb1d4db15.1655372759.git.jani.nikula@intel.com
parent 109406c9

drivers/gpu/drm/i915/display/intel_display.c

+1 −45
Original line number Diff line number Diff line
@@ -6582,50 +6582,6 @@ intel_verify_planes(struct intel_atomic_state *state) 
			     plane_state->uapi.visible);

}



static void

verify_mpllb_state(struct intel_atomic_state *state,

		   struct intel_crtc_state *new_crtc_state)

{

	struct drm_i915_private *i915 = to_i915(state->base.dev);

	struct intel_mpllb_state mpllb_hw_state = { 0 };

	struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;

	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);

	struct intel_encoder *encoder;



	if (!IS_DG2(i915))

		return;



	if (!new_crtc_state->hw.active)

		return;



	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);

	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);



#define MPLLB_CHECK(__name)						\

	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\

			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \

			crtc->base.base.id, crtc->base.name,		\

			__stringify(__name),				\

			mpllb_sw_state->__name, mpllb_hw_state.__name)



	MPLLB_CHECK(mpllb_cp);

	MPLLB_CHECK(mpllb_div);

	MPLLB_CHECK(mpllb_div2);

	MPLLB_CHECK(mpllb_fracn1);

	MPLLB_CHECK(mpllb_fracn2);

	MPLLB_CHECK(mpllb_sscen);

	MPLLB_CHECK(mpllb_sscstep);



	/*

	 * ref_control is handled by the hardware/firemware and never

	 * programmed by the software, but the proper values are supplied

	 * in the bspec for verification purposes.

	 */

	MPLLB_CHECK(ref_control);



#undef MPLLB_CHECK

}



static void

intel_modeset_verify_crtc(struct intel_crtc *crtc,

			  struct intel_atomic_state *state,
@@ -6639,7 +6595,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc, 
	verify_connector_state(state, crtc);

	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);

	intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);

	verify_mpllb_state(state, new_crtc_state);

	intel_mpllb_state_verify(state, new_crtc_state);

}



static void

drivers/gpu/drm/i915/display/intel_snps_phy.c

+43 −0
Original line number Diff line number Diff line
@@ -813,3 +813,46 @@ int intel_snps_phy_check_hdmi_link_rate(int clock) 


	return MODE_CLOCK_RANGE;

}



void intel_mpllb_state_verify(struct intel_atomic_state *state,

			      struct intel_crtc_state *new_crtc_state)

{

	struct drm_i915_private *i915 = to_i915(state->base.dev);

	struct intel_mpllb_state mpllb_hw_state = { 0 };

	struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;

	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);

	struct intel_encoder *encoder;



	if (!IS_DG2(i915))

		return;



	if (!new_crtc_state->hw.active)

		return;



	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);

	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);



#define MPLLB_CHECK(__name)						\

	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\

			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \

			crtc->base.base.id, crtc->base.name,		\

			__stringify(__name),				\

			mpllb_sw_state->__name, mpllb_hw_state.__name)



	MPLLB_CHECK(mpllb_cp);

	MPLLB_CHECK(mpllb_div);

	MPLLB_CHECK(mpllb_div2);

	MPLLB_CHECK(mpllb_fracn1);

	MPLLB_CHECK(mpllb_fracn2);

	MPLLB_CHECK(mpllb_sscen);

	MPLLB_CHECK(mpllb_sscstep);



	/*

	 * ref_control is handled by the hardware/firemware and never

	 * programmed by the software, but the proper values are supplied

	 * in the bspec for verification purposes.

	 */

	MPLLB_CHECK(ref_control);



#undef MPLLB_CHECK

}

drivers/gpu/drm/i915/display/intel_snps_phy.h

+4 −1
Original line number Diff line number Diff line
@@ -9,8 +9,9 @@ 
#include <linux/types.h>



struct drm_i915_private;

struct intel_encoder;

struct intel_atomic_state;

struct intel_crtc_state;

struct intel_encoder;

struct intel_mpllb_state;

enum phy;
@@ -31,5 +32,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, 
int intel_snps_phy_check_hdmi_link_rate(int clock);

void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,

				      const struct intel_crtc_state *crtc_state);

void intel_mpllb_state_verify(struct intel_atomic_state *state,

			      struct intel_crtc_state *new_crtc_state);



#endif /* __INTEL_SNPS_PHY_H__ */