Commit 78c3925c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull more ARM SoC updates from Arnd Bergmann:
 "These are changes that for some reason ended up not making it into the
  first four branches but that should still make it into 6.9:

   - A rework of the omap clock support that touches both drivers and
     device tree files

   - The reset controller branch changes that had a dependency on late
     bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
     drivers branch

   - The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
     changes that got delayed and needed some extra time in linux-next
     for wider testing"

* tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits)
  soc: fsl: dpio: fix kcalloc() argument order
  bus: ts-nbus: Improve error reporting
  bus: ts-nbus: Convert to atomic pwm API
  riscv: dts: starfive: jh7110: Add camera subsystem nodes
  ARM: bcm: stop selecing CONFIG_TICK_ONESHOT
  ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
  ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
  clk: ti: Improve clksel clock bit parsing for reg property
  clk: ti: Handle possible address in the node name
  dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
  dt-bindings: riscv: cpus: reg matches hart ID
  reset: Instantiate reset GPIO controller for shared reset-gpios
  reset: gpio: Add GPIO-based reset controller
  cpufreq: do not open-code of_phandle_args_equal()
  of: Add of_phandle_args_equal() helper
  reset: simple: add support for Sophgo SG2042
  dt-bindings: reset: sophgo: support SG2042
  riscv: dts: microchip: add specific compatible for mpfs pdma
  riscv: dts: microchip: add missing CAN bus clocks
  ARM: brcmstb: Add debug UART entry for 74165
  ...
parents f9c03549 72ebb41b

Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties: 
          - const: brcm,gisb-arb

      - items:

          - enum:

              - brcm,bcm74165-gisb-arb  # for V7 new style 16nm chips

              - brcm,bcm7278-gisb-arb  # for V7 28nm chips

              - brcm,bcm7435-gisb-arb  # for newer 40nm chips

              - brcm,bcm7400-gisb-arb  # for older 40nm chips and all 65nm chips

Documentation/devicetree/bindings/pwm/opencores,pwm.yaml

0 → 100644
+56 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: OpenCores PWM controller



maintainers:

  - William Qiu <william.qiu@starfivetech.com>



description:

  The OpenCores PTC ip core contains a PWM controller. When operating in PWM

  mode, the PTC core generates binary signal with user-programmable low and

  high periods. All PTC counters and registers are 32-bit.



allOf:

  - $ref: pwm.yaml#



properties:

  compatible:

    items:

      - enum:

          - starfive,jh7100-pwm

          - starfive,jh7110-pwm

          - starfive,jh8100-pwm

      - const: opencores,pwm-v1



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  resets:

    maxItems: 1



  "#pwm-cells":

    const: 3



required:

  - compatible

  - reg

  - clocks



additionalProperties: false



examples:

  - |

    pwm@12490000 {

        compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";

        reg = <0x12490000 0x10000>;

        clocks = <&clkgen 181>;

        resets = <&rstgen 109>;

        #pwm-cells = <3>;

    };

Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml

0 → 100644
+35 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2042 SoC Reset Controller



maintainers:

  - Chen Wang <unicorn_wang@outlook.com>



properties:

  compatible:

    const: sophgo,sg2042-reset



  reg:

    maxItems: 1



  "#reset-cells":

    const: 1



required:

  - compatible

  - reg

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    rstgen: reset-controller@c00 {

        compatible = "sophgo,sg2042-reset";

        reg = <0xc00 0xc>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/riscv/cpus.yaml

+4 −0
Original line number Diff line number Diff line
@@ -75,6 +75,10 @@ properties: 
      - riscv,sv57

      - riscv,none



  reg:

    description:

      The hart ID of this CPU node.



  riscv,cbom-block-size:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

MAINTAINERS

+5 −0
Original line number Diff line number Diff line
@@ -8987,6 +8987,11 @@ F: Documentation/i2c/muxes/i2c-mux-gpio.rst 
F:	drivers/i2c/muxes/i2c-mux-gpio.c

F:	include/linux/platform_data/i2c-mux-gpio.h









GENERIC GPIO RESET DRIVER









M:	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>









S:	Maintained









F:	drivers/reset/reset-gpio.c

















GENERIC HDLC (WAN) DRIVERS









M:	Krzysztof Halasa <khc@pm.waw.pl>









S:	Maintained