Commit 78e29356 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab Committed by Rob Herring
Browse files

dt-bindings: PCI: kirin: Convert kirin-pcie.txt to yaml 



Convert the file into a JSON description at the yaml format.

Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/081c179ef2e0ddf11566144cd5967b15268565b4.1628061310.git.mchehab+huawei@kernel.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 2de207f5

Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: HiSilicon Kirin SoCs PCIe host DT description



maintainers:

  - Xiaowei Song <songxiaowei@hisilicon.com>

  - Binghui Wang <wangbinghui@hisilicon.com>



description: |

  Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.

  It shares common functions with the PCIe DesignWare core driver and

  inherits common properties defined in

  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.



allOf:

  - $ref: /schemas/pci/snps,dw-pcie.yaml#



properties:

  compatible:

    contains:

      enum:

        - hisilicon,kirin960-pcie



  reg:

    description: |

      Should contain dbi, apb, config registers location and length.

      For HiKey960, it should also contain phy.

    minItems: 3

    maxItems: 4



  reg-names:

    minItems: 3

    maxItems: 4



required:

  - compatible

  - reg

  - reg-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/hi3660-clock.h>



    soc {

      #address-cells = <2>;

      #size-cells = <2>;



      pcie@f4000000 {

        compatible = "hisilicon,kirin960-pcie";

        reg = <0x0 0xf4000000 0x0 0x1000>,

              <0x0 0xff3fe000 0x0 0x1000>,

              <0x0 0xf3f20000 0x0 0x40000>,

              <0x0 0xf5000000 0x0 0x2000>;

        reg-names = "dbi", "apb", "phy", "config";

        bus-range = <0x0  0xff>;

        #address-cells = <3>;

        #size-cells = <2>;

        device_type = "pci";

        ranges = <0x02000000 0x0 0x00000000

                  0x0 0xf6000000

                  0x0 0x02000000>;

        num-lanes = <1>;

        #interrupt-cells = <1>;

        interrupts = <0 283 4>;

        interrupt-names = "msi";

        interrupt-map-mask = <0xf800 0 0 7>;

        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,

                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,

                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,

                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,

                 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,

                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,

                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,

                 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;

        clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",

                      "pcie_apb_sys", "pcie_aclk";

      };

    };

Documentation/devicetree/bindings/pci/kirin-pcie.txt

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HiSilicon Kirin SoCs PCIe host DT description



Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.

It shares common functions with the PCIe DesignWare core driver and

inherits common properties defined in

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.



Additional properties are described here:



Required properties

- compatible:

	"hisilicon,kirin960-pcie"

- reg: Should contain rc_dbi, apb, phy, config registers location and length.

- reg-names: Must include the following entries:

  "dbi": controller configuration registers;

  "apb": apb Ctrl register defined by Kirin;

  "phy": apb PHY register defined by Kirin;

  "config": PCIe configuration space registers.

- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.



Optional properties:



Example based on kirin960:



	pcie@f4000000 {

		compatible = "hisilicon,kirin960-pcie";

		reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,

		      <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;

		reg-names = "dbi","apb","phy", "config";

		bus-range = <0x0  0x1>;

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;

		num-lanes = <1>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <0x0 0 0 1 &gic 0 0 0  282 4>,

				<0x0 0 0 2 &gic 0 0 0  283 4>,

				<0x0 0 0 3 &gic 0 0 0  284 4>,

				<0x0 0 0 4 &gic 0 0 0  285 4>;

		clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,

			 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,

			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,

			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,

			 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;

		clock-names = "pcie_phy_ref", "pcie_aux",

			      "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";

		reset-gpios = <&gpio11 1 0 >;

	};

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

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@@ -35,7 +35,7 @@ properties: 
    maxItems: 5

    items:

      enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,

              ulreg, smu, mpu ]

              ulreg, smu, mpu, apb, phy ]



  num-lanes:

    description: |

MAINTAINERS

+1 −1
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@@ -14413,7 +14413,7 @@ M: Xiaowei Song <songxiaowei@hisilicon.com> 
M:	Binghui Wang <wangbinghui@hisilicon.com>

L:	linux-pci@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/kirin-pcie.txt

F:	Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml

F:	drivers/pci/controller/dwc/pcie-kirin.c









PCIE DRIVER FOR HISILICON STB